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Data retention structure for non-volatile memory / Unity Semiconductor Corporation




Title: Data retention structure for non-volatile memory.
Abstract: A data retention structure in a memory element that stores data as a plurality of conductivity profiles is disclosed. The memory element can be used in a variety of electrical systems and includes a conductive oxide layer, an ion impeding layer, and an electrolytic tunnel barrier layer. A write voltage applied across the memory element causes a portion of the mobile ions to move from the conductive oxide layer, through the ion impeding layer, and into the electrolytic tunnel barrier layer thereby changing a conductivity of the memory element, or the write voltage causes a quantity of the mobile ions to move from the electrolytic tunnel barrier layer, through the ion impeding layer, and back into the conductive oxide layer. The ion impeding layer is operative to substantially stop mobile ion movement when a voltage that is less than the write voltage is applied across the memory element. ...


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USPTO Applicaton #: #20120262981
Inventors: Lawrence Schloss


The Patent Description & Claims data below is from USPTO Patent Application 20120262981, Data retention structure for non-volatile memory.

CROSS-REFERENCE TO RELATED APPLICATIONS

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This application is a continuation of pending U.S. patent application Ser. No. 12/075,017, filed Mar. 7, 2008, the disclosure of which is herein incorporated by reference.

FIELD OF THE INVENTION

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The present invention relates generally to non-volatile memory. More specifically, the present invention relates to thin-film structures in non-volatile memory.

BACKGROUND

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OF THE INVENTION

Data storage in high-density memory devices can be accomplished using a variety of techniques. Often, the technique used depends on whether or not the stored data is volatile or non-volatile. In volatile memory devices, such as SRAM and DRAM, for example, stored data is not retained when power is removed from the memory device. On the other hand, for non-volatile memory devices, such as MRAM and Flash devices, stored data is retained when power is removed from the memory device.

Resistive state memory devices are a promising new type of non-volatile memory in which data is stored in a memory element as a plurality of conductivity profiles (e.g., distinct resistive states). A first conductivity profile can represent a logic “1” and a second conductivity profile can represent a logic “0”. The first and second conductivity profiles can be set by applying a write voltage of a predetermined magnitude, polarity, and duration across the memory element during a write operation. For example, voltage pulses can be used to write a logic “1” and a logic “0”, respectively.

In either case, after data has been written to the memory element, reading the value of the stored data in the memory element is typically accomplished by applying a read voltage across the memory element and sensing a read current that flows through the memory element. For example, if a logic “0” represents a high resistance and a logic “1” represents a low resistance, then for a constant read voltage, a magnitude of the read current can be indicative of the resistive state of the memory element. Therefore, based on Ohm's law, the read current will be low if the data stored is a logic “0” (e.g., high resistance) or the read current will be high if the data stored is a logic “1” (e.g., low resistance). Consequently, the value of the stored data can be determined by sensing the magnitude of the read current.

In high density memory devices, it is desirable to pack as many memory cells as possible in the smallest area possible in order to increase memory density and data storage capacity. One factor that can have a significant impact on memory density is the number of terminals that are required to access a memory element for reading or writing. As the number of terminals required to access the memory element increases, device area increases with a concomitant decrease in areal density. Most memory technologies, such as DRAM, SRAM, and some MRAM devices, require at least three terminals to access the core memory element that stores the data. However, in some memory technologies, such as certain resistance based memories, two terminals can be used to both read and write data to/from the memory element.

An array of two terminal memory elements can include a plurality of row conductors and a plurality of column conductors and each memory element can have a terminal connected with one of row conductors and the other terminal connected with one of the column conductors. The typical arrangement is a two terminal cross-point memory array where each memory element is positioned approximately at an intersection of one of the row conductors with one of the column conductors. The terminals of the memory element connect with the row and column conductors above and below it. A single memory element can be written by applying the write voltage across the row and column conductors the memory element is connected with. Similarly, the memory element can be read by applying the read voltage across the row and column conductors the memory element is connected with. The read current can be sensed (e.g., measured) flowing through the row conductor or the column conductor.

One challenge for some non-volatile memories is data retention, that is, the ability of stored data to be retained in the absence of power. Ideally, stored data is retained indefinitely in the absence of power. Examples of factors affecting data retention include but are not limited to memory element structure, material used in the memory element, and voltages applied across the memory elements during data operations, such as read and write operations. When a read or write voltage is applied across the two terminals of a selected memory element, approximately half of the voltage potential is supplied by the row conductor and half by the column conductor. Accordingly, other memory elements having a terminal connected with the row conductor or column conductor also have a voltage potential applied across their respective terminals. Those un-selected memory elements are generally referred to as half-selected memory elements because one of their terminals has ½ of a read voltage potential or ½ of a write voltage potential applied to it and the other terminal is typically at a ground potential. The potential difference across the terminals is referred to as a half-select voltage. The half-select voltage can generate electric fields, that over time, can disturb (e.g., corrupt) the stored data in those memory elements. Moreover, because write voltages are typically greater in magnitude than read voltages, the half-select voltages during write operations are greater than the half-select voltages during read operations. Therefore, it is desirable for the write voltages to affect stored data only in the selected memory element(s) and not in half-selected memory elements.

Although the magnitude of half-select voltages may be lower for read operations, in some applications, a majority of data operations to a non-volatile memory may comprise read operations. Repeated read operations may result in numerous applications of read voltages and half-select voltages to memory elements in a memory device. The application of half-select voltages during read operation may affect data retention in half-selected memory elements. However, those skilled in the art will appreciate that some design choices will affect the extent an array is exposed to half-select voltages. For example, a page mode read might not cause the array to experience any half-select voltages during read operations.

There are continuing efforts to improve non-volatile memory.

BRIEF DESCRIPTION OF THE DRAWINGS

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FIG. 1 depicts a memory element including mobile ions and storing data as a first conductivity profile;

FIG. 2A depicts a memory element switching from a first conductivity profile to a second conductivity profile;

FIG. 2B depicts a memory element having the second conductivity profile;

FIG. 2C depicts retention of the second conductivity profile;

FIG. 3A depicts a memory element switching from the second conductivity profile to the first conductivity profile;

FIG. 3B depicts a memory element having the first conductivity profile;

FIG. 3C depicts retention of the first conductivity profile;

FIG. 4A depicts a memory element having a second conductivity profile that is unaffected by application of a first read voltage;

FIG. 4B depicts a memory element having a first conductivity profile that is unaffected by application of the first read voltage;

FIG. 4C depicts a memory element having a second conductivity profile that is unaffected by application of a second read voltage;

FIG. 4D depicts a memory element having a first conductivity profile that is unaffected by application of the second read voltage;

FIG. 5 depicts a memory element electrically in series with and sandwiched by a pair of electrodes;

FIG. 6A depicts a non-ohmic device and a memory element that are electrically in series with and sandwiched between a pair of electrodes;

FIG. 6B depicts an alternate configuration of a non-ohmic device and a memory element that are electrically in series with and sandwiched between a pair of electrodes;

FIG. 7A depicts a portion of a non-volatile two-terminal cross-point array including a non-volatile memory plug electrically in series with a first conductive array line and a second conductive array line;

FIG. 7B depicts a schematic view of a non-volatile two-terminal cross-point array that includes a plurality of memory plugs;

FIG. 7C depicts selected, half-selected, and un-selected memory plugs in a non-volatile two-terminal cross-point array;

FIG. 8A is a cross-sectional view depicting a non-volatile two-terminal cross-point array positioned over a substrate that includes active circuitry;

FIG. 8B is a cross-sectional view depicting a stacked non-volatile two-terminal cross-point array positioned over a substrate that includes active circuitry;




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stats Patent Info
Application #
US 20120262981 A1
Publish Date
10/18/2012
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
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Drawings
0




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Unity Semiconductor Corporation


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20121018|20120262981|data retention structure for non-volatile memory|A data retention structure in a memory element that stores data as a plurality of conductivity profiles is disclosed. The memory element can be used in a variety of electrical systems and includes a conductive oxide layer, an ion impeding layer, and an electrolytic tunnel barrier layer. A write voltage |Unity-Semiconductor-Corporation
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