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Data retention structure for non-volatile memory

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Data retention structure for non-volatile memory


A data retention structure in a memory element that stores data as a plurality of conductivity profiles is disclosed. The memory element can be used in a variety of electrical systems and includes a conductive oxide layer, an ion impeding layer, and an electrolytic tunnel barrier layer. A write voltage applied across the memory element causes a portion of the mobile ions to move from the conductive oxide layer, through the ion impeding layer, and into the electrolytic tunnel barrier layer thereby changing a conductivity of the memory element, or the write voltage causes a quantity of the mobile ions to move from the electrolytic tunnel barrier layer, through the ion impeding layer, and back into the conductive oxide layer. The ion impeding layer is operative to substantially stop mobile ion movement when a voltage that is less than the write voltage is applied across the memory element.

Browse recent Unity Semiconductor Corporation patents - Sunnyvale, CA, US
Inventor: Lawrence Schloss
USPTO Applicaton #: #20120262981 - Class: 365148 (USPTO) - 10/18/12 - Class 365 


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The Patent Description & Claims data below is from USPTO Patent Application 20120262981, Data retention structure for non-volatile memory.

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CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of pending U.S. patent application Ser. No. 12/075,017, filed Mar. 7, 2008, the disclosure of which is herein incorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to non-volatile memory. More specifically, the present invention relates to thin-film structures in non-volatile memory.

BACKGROUND OF THE INVENTION

Data storage in high-density memory devices can be accomplished using a variety of techniques. Often, the technique used depends on whether or not the stored data is volatile or non-volatile. In volatile memory devices, such as SRAM and DRAM, for example, stored data is not retained when power is removed from the memory device. On the other hand, for non-volatile memory devices, such as MRAM and Flash devices, stored data is retained when power is removed from the memory device.

Resistive state memory devices are a promising new type of non-volatile memory in which data is stored in a memory element as a plurality of conductivity profiles (e.g., distinct resistive states). A first conductivity profile can represent a logic “1” and a second conductivity profile can represent a logic “0”. The first and second conductivity profiles can be set by applying a write voltage of a predetermined magnitude, polarity, and duration across the memory element during a write operation. For example, voltage pulses can be used to write a logic “1” and a logic “0”, respectively.

In either case, after data has been written to the memory element, reading the value of the stored data in the memory element is typically accomplished by applying a read voltage across the memory element and sensing a read current that flows through the memory element. For example, if a logic “0” represents a high resistance and a logic “1” represents a low resistance, then for a constant read voltage, a magnitude of the read current can be indicative of the resistive state of the memory element. Therefore, based on Ohm\'s law, the read current will be low if the data stored is a logic “0” (e.g., high resistance) or the read current will be high if the data stored is a logic “1” (e.g., low resistance). Consequently, the value of the stored data can be determined by sensing the magnitude of the read current.

In high density memory devices, it is desirable to pack as many memory cells as possible in the smallest area possible in order to increase memory density and data storage capacity. One factor that can have a significant impact on memory density is the number of terminals that are required to access a memory element for reading or writing. As the number of terminals required to access the memory element increases, device area increases with a concomitant decrease in areal density. Most memory technologies, such as DRAM, SRAM, and some MRAM devices, require at least three terminals to access the core memory element that stores the data. However, in some memory technologies, such as certain resistance based memories, two terminals can be used to both read and write data to/from the memory element.

An array of two terminal memory elements can include a plurality of row conductors and a plurality of column conductors and each memory element can have a terminal connected with one of row conductors and the other terminal connected with one of the column conductors. The typical arrangement is a two terminal cross-point memory array where each memory element is positioned approximately at an intersection of one of the row conductors with one of the column conductors. The terminals of the memory element connect with the row and column conductors above and below it. A single memory element can be written by applying the write voltage across the row and column conductors the memory element is connected with. Similarly, the memory element can be read by applying the read voltage across the row and column conductors the memory element is connected with. The read current can be sensed (e.g., measured) flowing through the row conductor or the column conductor.

One challenge for some non-volatile memories is data retention, that is, the ability of stored data to be retained in the absence of power. Ideally, stored data is retained indefinitely in the absence of power. Examples of factors affecting data retention include but are not limited to memory element structure, material used in the memory element, and voltages applied across the memory elements during data operations, such as read and write operations. When a read or write voltage is applied across the two terminals of a selected memory element, approximately half of the voltage potential is supplied by the row conductor and half by the column conductor. Accordingly, other memory elements having a terminal connected with the row conductor or column conductor also have a voltage potential applied across their respective terminals. Those un-selected memory elements are generally referred to as half-selected memory elements because one of their terminals has ½ of a read voltage potential or ½ of a write voltage potential applied to it and the other terminal is typically at a ground potential. The potential difference across the terminals is referred to as a half-select voltage. The half-select voltage can generate electric fields, that over time, can disturb (e.g., corrupt) the stored data in those memory elements. Moreover, because write voltages are typically greater in magnitude than read voltages, the half-select voltages during write operations are greater than the half-select voltages during read operations. Therefore, it is desirable for the write voltages to affect stored data only in the selected memory element(s) and not in half-selected memory elements.

Although the magnitude of half-select voltages may be lower for read operations, in some applications, a majority of data operations to a non-volatile memory may comprise read operations. Repeated read operations may result in numerous applications of read voltages and half-select voltages to memory elements in a memory device. The application of half-select voltages during read operation may affect data retention in half-selected memory elements. However, those skilled in the art will appreciate that some design choices will affect the extent an array is exposed to half-select voltages. For example, a page mode read might not cause the array to experience any half-select voltages during read operations.

There are continuing efforts to improve non-volatile memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a memory element including mobile ions and storing data as a first conductivity profile;

FIG. 2A depicts a memory element switching from a first conductivity profile to a second conductivity profile;

FIG. 2B depicts a memory element having the second conductivity profile;

FIG. 2C depicts retention of the second conductivity profile;

FIG. 3A depicts a memory element switching from the second conductivity profile to the first conductivity profile;

FIG. 3B depicts a memory element having the first conductivity profile;

FIG. 3C depicts retention of the first conductivity profile;

FIG. 4A depicts a memory element having a second conductivity profile that is unaffected by application of a first read voltage;

FIG. 4B depicts a memory element having a first conductivity profile that is unaffected by application of the first read voltage;

FIG. 4C depicts a memory element having a second conductivity profile that is unaffected by application of a second read voltage;

FIG. 4D depicts a memory element having a first conductivity profile that is unaffected by application of the second read voltage;

FIG. 5 depicts a memory element electrically in series with and sandwiched by a pair of electrodes;

FIG. 6A depicts a non-ohmic device and a memory element that are electrically in series with and sandwiched between a pair of electrodes;

FIG. 6B depicts an alternate configuration of a non-ohmic device and a memory element that are electrically in series with and sandwiched between a pair of electrodes;

FIG. 7A depicts a portion of a non-volatile two-terminal cross-point array including a non-volatile memory plug electrically in series with a first conductive array line and a second conductive array line;

FIG. 7B depicts a schematic view of a non-volatile two-terminal cross-point array that includes a plurality of memory plugs;

FIG. 7C depicts selected, half-selected, and un-selected memory plugs in a non-volatile two-terminal cross-point array;

FIG. 8A is a cross-sectional view depicting a non-volatile two-terminal cross-point array positioned over a substrate that includes active circuitry;

FIG. 8B is a cross-sectional view depicting a stacked non-volatile two-terminal cross-point array positioned over a substrate that includes active circuitry;

FIG. 9 is a table depicting data for erase and program slopes for memory elements with and without ion impeding layers;

FIG. 10 is a plot depicting current loss over time for memory elements with and without ion impeding layers;

FIG. 11 depicts a memory system including a non-volatile two-terminal cross-point array; and

FIG. 12 depicts an exemplary electrical system that includes at least one non-volatile two-terminal cross-point array with a data retention structure for data storage.

Although the previous drawings depict various examples of the invention, the invention is not limited by the depicted examples. Furthermore, the depictions are not necessarily to scale.

DETAILED DESCRIPTION

In the following detailed description and in the several figures of the drawings, like elements are identified with like reference numerals.

As shown in the drawings for purpose of illustration, the present invention is embodied in a non-volatile memory device, a non-volatile memory element, and a non-volatile memory array.

Reference is now made to FIG. 1 and similarly as in FIG. 3D where a non-volatile memory device 100 includes a memory element 120. The memory element 120 includes a conductive oxide layer 101, an ion impeding layer, and an electrolytic tunnel barrier layer 105. The layers 101, 103, and 105 of the memory element 120 are electrically in series with one another. Preferably, surfaces 101b, 101t, 103t, and 105t of the layers 101, 103, and 105 are substantially planar surfaces or share the same undulations and have substantially uniform thickness t1, t2, and t3, respectively.

The conductive oxide layer 101 includes mobile ions 111 that are movable between the electrolytic tunnel barrier layer 105 and the conductive oxide layer 101 in response to an electric field having a predetermined magnitude and direction, as will be described in greater detail below. The conductive oxide layer 101 can be a conductive perovskite. Examples of conductive perovskites include but are not limited to PCMO, LNO, LCMO, LSCO, LSMO, PMO, strontium titanate (STO), and a reduced STO. The thickness t3 of the conductive oxide layer 101 will be application specific. For example, an approximate range of thicknesses can be from about 100 Å to about 300 Å. As one example, the thickness t3 can be approximately 250 Å. The conductive oxide layer 101 can be formed using microelectronics fabrication techniques that are well understood in the semiconductor art for forming thin films. Example fabrication techniques include but are not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, molecular beam epitaxy (MBE), spin-on deposition, pulsed laser deposition, electron-beam (e-beam) deposition, and thermal evaporation.

The ion impeding layer 103 is configured to substantially stop ion movement between the electrolytic tunnel barrier layer 105 and the conductive oxide layer 101 when a voltage that is less than a predetermined magnitude is applied across the memory element 120, as will be described in greater detail below. The material selected for the ion impeding layer 103 will be application dependent. However, suitable materials for the ion impeding layer 103 include but are not limited to LaAlO3, TiOx, TaOx, AlOx, SiC, SiOx, IrOx, MgO, Pt, strontium ruthenate (SRO), and a reduced SRO.

Criteria for selecting the material for ion impeding layer 103 may include but are not limited to a material operative as a mobility barrier to the mobile ions 111, a material having a high activation energy for migration of mobile ions 111 to vacancy sites in the material, a material having stoichiometrically too few sites for migration of the mobile ions 111, and a material having a low conductivity to the mobile ions 111 and having an electrical conductivity that is higher that an electrical conductivity of a material for the electrolytic tunnel barrier layer 105.

The electrolytic tunnel barrier layer 105 is made from an insulating material (e.g., a dielectric material) that allows ion movement. Those skilled in the art will appreciate that the term electronic refers to electron or hole movement, while the term electrical or electrolyte refers to ion movement. Accordingly, an electrolytic tunnel barrier is a material with bulk properties of an electronic insulator that allows ionic movement but is thin enough to allow for electron tunneling. Suitable materials for the electrolytic tunnel barrier layer 105 include but are not limited to yttria-stabilized zirconia (YSZ), ZrO2, HfO2, and Er2O3. The electrolytic tunnel barrier layer 105 is operative to provide electron tunneling such that the memory element 120 has a non-linear I-V curve and the current flowing through the memory element 120 is a non-linear function of the voltage applied across the memory element 120. Tunneling mechanism for the electrolytic tunnel barrier layer 105 include but are not limited to single step tunneling processes (e.g., direct tunneling, Fowler-Nordheim tunneling, and thermionic field emission tunneling) and multi-step tunneling processes (e.g., trap-assisted tunneling).

The material and thickness t1 for the electrolytic tunnel barrier layer 105 will be application dependent. Preferably, the thickness t1 of the electrolytic tunnel barrier layer 105 is approximately 100 Å or less. More preferably, the thickness t1 is approximately 50 Å or less. For example, the thickness t1 can be approximately 25 Å. If the electrolytic tunnel barrier layer 105 is too thick, tunneling may not occur or the voltage across the memory element 120 necessary for tunneling may be too high. For example, currents generated by the applied voltage may exceed current density limitations of the memory element and/or conductive array lines, the resulting electric field generated by the applied voltage may exceed breakdown limits of the thin film materials in the memory element, or the magnitude of the applied voltage may require driver circuitry that exceeds an area budget for a memory design. The thickness t2 for the ion impeding layer 103 is approximately no greater than the thickness t1 for the electrolytic tunnel barrier layer 105 (e.g., t2≦t1). If the ion impeding layer 103 is too thick, device currents may be too low and/or the mobile ions 111 may not be able to travel through the ion impeding layer 103. For example, the thickness t2 for the ion impeding layer 103 can be approximately 20 Å. As another example, if the ion impeding layer 103 is made from silicon carbide (SiC), then the thickness t2 can be approximately 10 Å. The ion impeding layer 103 and the electrolytic tunnel barrier layer 105 may be formed using the fabrication techniques described above for the conductive oxide layer 101.

Referring again to FIG. 1, the memory element 120 stores data as a plurality of conductivity profiles (e.g., resistive states). One of the conductivity profiles may be indicative of a first resistive state (e.g., a logic 1 or an erased state) and another one of the conductivity profiles may be indicative of a second resistive state (e.g., a logic 0 or a programmed state). For example, in FIG. 1 the mobile ions 111 are positioned in the conductive oxide layer 101 and the memory element 120 can store data as the first conductivity profile (e.g., erased state or logic 1). Turning now to FIG. 2A, a first write configuration 200 includes a voltage source 201 operative to apply a first write voltage VW1 across the memory element 120. A switch 203 is connected with the voltage source 201 and is operative to apply the first write voltage VW1 across the memory element 120. Conversely, when the switch 203 is open the first write voltage VW1 is no longer applied across the memory element 120. As depicted in FIG. 2A, the switch 203 is closed so that the first write voltage VW1 is applied across the memory element 120 at nodes 202 and 204. A magnitude and polarity of the first write voltage VW1 is operative to generate a first electric field E1 having a magnitude sufficient to cause a quantity of the mobile ions 111 to move from the conductive oxide layer 101, through the ion impeding layer 103, and into the electrolytic tunnel barrier layer 105. Those skilled in the art will appreciate that the first electric field E1 has a plurality of magnitudes depending on the dielectric constant and conductivity of the specific materials being used for the memory element 120. Based on the direction of the first electric field E1 and on the direction of movement of the mobile ions 111, the mobile ions 111 depicted in FIG. 2A have a negative charge and move in a direction that is opposite that of the first electric field E1. For example, the mobile ions 111 can be negatively charged oxygen ions (O−). However, the charge of the mobile ions 111 is not limited to negatively charge species of ions and in some applications the mobile ions 111 may be positively charged ions.

Moving now to FIG. 2B, a quantity 211 of the mobile ions 111 have moved from the conductive oxide layer 101, through the ion impeding layer 103, and into the electrolytic tunnel barrier layer 105 after the first electric field E1 was applied. Reference to a quantity may include some or all of the mobile ions 111. The switch 203 is opened and the first write voltage VW1 is no longer applied across the memory element 120. The ion impeding layer 103 is operative to substantially stop (see dashed arrows 205) the quantity 211 from moving back through the ion impeding layer 103 and into the conductive oxide layer 101 unless a write voltage having a sufficient magnitude and polarity (e.g., a second write voltage as will be described below) is applied across the memory element 120. In FIG. 2B, the voltage applied across the memory element 120 is substantially 0V; however, as will be described below, a read voltage having a magnitude that is less than the write voltage can be applied across the memory element 120. The ion impeding layer 103 is further operative to substantially stop movement of the quantity 211 when the read voltage is applied across nodes (202, 204). Moreover, when the memory element 120 is half-selected such that a half-select voltage is applied across the nodes (202, 204) the ion impeding layer 103 is also operative to substantially stop movement of the quantity 211. It should be appreciated by those skilled in the art that the term “quantity” refers only to those ions that are impeded by the ion impeding layer 103 and not any ions that may not be impeded.

The relocation of the mobile ions 111 in the conductive oxide layer 101 to the electrolytic tunnel barrier layer 105 (i.e., quantity 211) results in a change in electrical conductivity of the memory element 120 such that its conductivity profile is switched from the first conductivity profile present in FIG. 1 to a second conductivity profile present in FIGS. 2B and 2C. Accordingly, the application of the first write voltage VW1 has effectuated a writing of new data to the memory element 120 and the second conductivity profile is indicative of the new data. In one embodiment, the second conductivity profile is indicative of a logic 0 or a programmed state of the memory element 120.



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stats Patent Info
Application #
US 20120262981 A1
Publish Date
10/18/2012
Document #
13532381
File Date
06/25/2012
USPTO Class
365148
Other USPTO Classes
International Class
11C11/00
Drawings
14



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