Logic circuit and method of logic circuit design   

Abstract: A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal.

This application is a continuation of U.S. patent application Ser. No. 12/758,072 filed on Apr. 12, 2010, which is a continuation of U.S. patent application Ser. No. 11/826,281 filed on Jul. 13, 2007, now U.S. Pat. No. 7,716,625, which is a divisional of U.S. patent application Ser. No. 10/648,474 filed on Aug. 27, 2003, now U.S. Pat. No. 7,345,511, which claims the benefit of priority of U.S. Provisional Patent Application No. 60/406,751 filed on Aug. 29, 2002. The contents of the above applications are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a logic circuit design and, more particularly, to a logic circuit design for combinatorial and asynchronous logic circuits.

A large body of research has been performed to develop and improve traditional Complementary Metal Oxide Semiconductor (CMOS) techniques for the production of integrated circuits (ICs). The object of this research is to develop a faster, lower power, and reduced area alternative to standard CMOS logic circuits (see A. P. Chandrakasan, S. Sheng, R. W. Brodersen, “Low-Power CMOS Digital Design”, IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473-484, April 1992, and in A. P. Chandrakasan, R. W. Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, April 1995.) This research has resulted in the development of many logic design techniques during the last two decades. One popular alternative to CMOS is pass-transistor logic (PTL).

Formal methods for deriving pass-transistor logic are known for Negative-channel Metal Oxide Semiconductor (NMOS) transistors. The logic circuits resulting from these known methods yield an NMOS PTL logic circuit having a set of control signals applied to the gates of NMOS transistors, and a set of data signals applied to the sources of the n-transistors. Many PTL circuit implementations have been proposed in the literature (see also W. Al-Assadi, A. P. Jayasumana and Y. K. Malaiya, “Pass-transistor logic design”, International Journal of Electronics, 1991, vol. 70, no. 4, pp. 739-749, K. Yano, Y. Sasaki, K. Rikino, K. Seki. “Top-Down Pass-Transistor Logic Design”, IEEE Journal of Solid-State Circuits, vol. 31, no. 6, pp. 792-803, June 1996, R. Zimmermann, W. Fichtner, “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, June 1997, and K. Bernstein, L. M. Carrig, C. M. Durham and P. A. Hansen, “High Speed CMOS Design Styles”, Kluwer Academic Press, 1998, and K. Bernstein, L. M. Carrig, C. M. Durham and P. A. Hansen, “High Speed CMOS Design Styles”, Kluwer Academic Press, 1998).

Some of the main advantages of PTL over standard CMOS design are: high speed due to the small node capacitances; low power dissipation as a result of the reduced number of transistors; and lower interconnection effects due to a small area.

Most PTL implementations, however, have two basic problems. First, the threshold drop across the single-channel pass transistors results in reduced current drive and hence slower operation at reduced supply voltages. This drop is particularly important for low power design since it is desirable to operate at the lowest possible voltage level. Second, since the input voltage for a high logic level at the regenerative inverters is not VDD, the PMOS device in the inverter is not fully turned off, and hence direct-path static power dissipation can be significant.

There are many PTL techniques that attempt to solve the problems mentioned above. Some of them are: Transmission Gate CMOS (TG), Complementary Pass-transistor Logic (CPL), and Double Pass-transistor Logic (DPL). TG uses transmission gate logic to realize complex logic functions using a small number of complementary transistors. TG solves the problem of low logic level swing by using PMOS as well as NMOS transistors. CPL features complementary inputs/outputs using NMOS pass-transistor logic with CMOS output inverters. CPL\'s most important feature is the small stack height and the internal node low swing, which contribute to lowering the power consumption. The CPL technique suffers from static power consumption due to the low swing at the gates of the output inverters. To lower the power consumption of CPL circuits, latched complementary pass-transistor logic (LCPL) and swing restored pass-transistor logic (SRPL) circuit styles are used. These styles contain PMOS restoration transistors or cross-coupled inverters respectively. DPL uses complementary transistors to keep full swing operation and reduce the DC power consumption, eliminating the need for restoration circuitry. One disadvantage of DPL is the large area required by the presence of PMOS transistors.

An additional problem of existing PTL is the top-down logic design complexity, which prevents the pass-transistors from capturing a major role in real logic large-scale integration technology (LSI). One of the main reasons for this is that no simple and universal cell library is available for PTL based design. Not all variations of input values to a basic PTL cell produce well-defined logic values. This creates difficulties in the development of automatic design systems for PTL logic, and in the verification of PTL logic circuit performance.

Asynchronous logic design has been established as a competitive alternative to synchronous circuits thanks to the potential for high-speed, low-power, reduced electromagnetic interference, and timing modularity (see J. Sparsø and S. Furber (eds.), Principles of asynchronous circuit design—A systems perspective, Kluwer Academic Publishers, 2001). Asynchronous logic has been developed in the last decade to deal with the challenges posed by the progress of very large-scale integration (VLSI) technologies, together with the increasing number of gates on chip, high density, and GHz operation frequencies. These problems are expected to appear in future high-performance technologies operating at the 10 GHz bather, due to the increased influence of interconnect on signal delay, uncertainty in the delay of a given gate, and on-chip parameter variations. These factors create difficulties in the design of fast digital systems controlled by a single general clock, due to considerations of delay skew between distant logic blocks, as well as the complexity of design of structures controlled by multiple clocks.

Asynchronous design provides digital systems based on self-timed circuits, which demand no control of a general clock, along with fast communication protocols in which speed depends only on the self delay of the logic gates. The absence of a general clock contributes to low power operation, by eliminating the concentrated power consumption of certain chip areas where numerous transactions occur with arrival of each clock signal.

However, these desirable characteristics usually come at a cost of either silicon area, or speed, or power, and cannot be achieved all at once. Furthermore, asynchronous circuits are typically more complicated than their synchronous counterparts. Although many researchers have sought efficient asynchronous circuit implementations, the disadvantages of current asynchronous logic techniques have not yet been overcome.

There is thus a widely recognized need for, and it would be highly advantageous to have, a digital logic circuit devoid of the above limitations.

SUMMARY

According to a first aspect of the present invention there is provided a complementary logic circuit containing a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal.

Preferably, the first and second logic inputs are connected to form a first common logic input.

Preferably, each of the logic terminals is separately configurable to serve as a logic input.

Preferably, each of the logic terminals is separately configurable to serve as a logic output.

Preferably, the logic circuit further contains a third logic input connected to a second network gate connection of the p-type transistor network.

Preferably, the logic circuit further contains a fourth logic input connected to a second network gate connection of the n-type transistor network.

Preferably, the third and fourth logic inputs are connected to form a second common logic input.

Preferably, the p-type transistor network comprises a single p-type transistor.

Preferably, the n-type transistor network comprises a single n-type transistor.

Preferably, the network of p-type transistors comprises one of a group of networks comprising: a network of p-type field effect transistors (FET), a network of p-type p-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type n-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type twin-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type silicon on insulator (SOI) transistors, and a network of p-type silicon on sapphire (SOS) transistors.

Preferably, the network of n-type transistors comprises one of a group of networks comprising: a network of n-type FETs, a network of n-type p-well CMOS transistors, a network of n-type n-well CMOS transistors, a network of n-type twin-well CMOS transistors, a network of n-type SOI transistors, and a network of n-type SOS transistors.

Preferably, the logic circuit comprises one of a group of the following logic circuits: an OR gate, an inverted OR (NOR) gate, an AND gate, a multiplexer gate, an inverter gate, and an exclusive OR (XOR) gate.

Preferably, the logic circuit is operable to implement a ((NOT A) OR B) logic operation upon logic inputs A and B.

Preferably, the logic circuit is operable to implement a ((NOT A) AND B) logic operation upon logic inputs A and B.

According to a second aspect of the present invention there is provided a logic circuit consisting of interconnected logic elements. Each of the logic elements contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a p-type transistor having an outer diffusion connection, a gate connection, and an inner diffusion connection, and an n-type transistor having an outer diffusion connection, a gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor is connected to the first dedicated logic terminal, and the gate connection of the p-type transistor is connected to the first logic input. The outer diffusion connection of the n-type transistor is connected to the second dedicated logic terminal, and the gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type and the n-type transistors are connected together to form a common diffusion logic terminal.

Preferably, for each of logic elements the first and second logic inputs are connected to form a common logic input.

Preferably, for each of logic elements each of the logic terminals is separately configurable to serve as a logic input.

Preferably, for each of logic elements each of the logic terminals is separately configurable to serve as a logic output.

Preferably, the type of the p-type transistors comprises one of a group of transistor types comprising: p-type FET transistors, p-type p-well CMOS transistors, p-type n-well CMOS transistors, p-type twin-well CMOS transistors, p-type SOI transistors, and p-type SOS transistors.

Preferably, the type of n-type transistors comprises one of a group of transistor types comprising: n-type FET transistors, n-type p-well CMOS transistors, n-type n-well CMOS transistors, n-type twin-well CMOS transistors, n-type SOI transistors, and n-type SOS transistors.

Preferably, the logic circuit is one of a group of logic circuits including: an OR gate, an inverted OR (NOR) gate, an AND gate, a multiplexer gate, an inverter gate, and an exclusive OR (XOR) gate.

Preferably, the logic circuit is operable to implement a ((NOT A) OR B) logic operation upon logic inputs A and B.

Preferably, the logic circuit is operable to implement a ((NOT A) AND B) logic operation upon logic inputs A and B.

Preferably, the logic circuit further contains at least one stabilizing buffer element.

Preferably, the logic circuit further contains at least one inverter.

Preferably, the logic circuit comprises a C-element.

Preferably, the logic circuit comprises a latch.

Preferably, the logic circuit is one of a group of logic circuits including: an SR latch, a D latch, a T latch, and a toggle flip-flop (TFF).

Preferably, the logic circuit comprises a bundle data filter controller.

Preferably, the logic circuit comprises a one to two decoder.

Preferably, the logic circuit is one of a group of logic circuits including: a carry-lookahead adder (CLA), a ripple adder, a combined ripple-CLA adder, a ripple comparator, a multiplier, and a counter.

According to a third aspect of the present invention there is provided a logic circuit, consisting of interconnected logic elements. Each of the logic elements contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal.

Preferably, for each of the logic elements the first and second logic inputs are connected to form a first common logic input.

Preferably, for each of the logic elements each of the logic terminals is separately configurable to serve as a logic input.

Preferably, for each of the logic elements each of the logic terminals is separately configurable to serve as a logic output.

Preferably, the logic circuit further contains a third logic input connected to a second network gate connection of the p-type transistor network.

Preferably, the logic circuit further contains a fourth logic input connected to a second network gate connection of the n-type transistor network.

Preferably, the third and fourth logic inputs are connected to form a second common logic input.

Preferably, the p-type transistor network comprises a single p-type transistor.

Preferably, the n-type transistor network comprises a single n-type transistor.

Preferably, the network of p-type transistors comprises one of a group of networks comprising: a network of p-type field effect transistors (FET), a network of p-type p-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type n-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type twin-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type silicon on insulator (SOI) transistors, and a network of p-type silicon on sapphire (SOS) transistors.

Preferably, the network of n-type transistors comprises one of a group of networks comprising: a network of n-type FETs, a network of n-type p-well CMOS transistors, a network of n-type n-well CMOS transistors, a network of n-type twin-well CMOS transistors, a network of n-type SOI transistors, and a network of n-type SOS transistors.

Preferably, the logic circuit further contains at least one buffer element.

Preferably, the logic circuit further contains at least one inverter.

According to a fourth aspect of the present invention there is provided a method for designing a logic circuit for performing a given logic function. The logic circuit to be constructed from interconnected logic elements. Each of the logic elements contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a p-type transistor having an outer diffusion connection, a gate connection, and an inner diffusion connection, and an n-type transistor having an outer diffusion connection, a gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor is connected to the first dedicated logic terminal, and the gate connection of the p-type transistor is connected to the first logic input. The outer diffusion connection of the n-type transistor is connected to the second dedicated logic terminal, and the gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type and the n-type transistors are connected together to form a common diffusion logic terminal. The method is performed by setting a synthesized function equal to the given logic function, and performing a synthesis recursion cycle. The synthesis recursion cycle consists of the following steps: if the synthesized function comprises a single non-inverted logic variable, providing a logic circuit design comprising an input terminal for the non-inverted logic variable and discontinuing the synthesis recursion cycle; if the synthesized function comprises a high logic signal, providing a logic circuit design comprising a connection to a high logic level, and discontinuing the synthesis recursion cycle; if the synthesized function comprises a low logic signal, providing a logic circuit design comprising a connection to a low logic level, and discontinuing the synthesis recursion cycle; and if the synthesized function comprises either an inverted single variable or a multi-variable function, performing the following sequence of steps. The sequence of steps is: extracting a first logic function, and a second logic function from a Shannon expansion of the synthesized function for a selected logic variable; setting the synthesized function to the first logic function; performing a synthesis recursion cycle to obtain a circuit design for a first sub-circuit; setting the synthesized function to the second logic function; performing a synthesis recursion cycle to obtain a circuit design for a second sub-circuit; providing a logic circuit design comprising a logic element having an input terminal for the selected logic variable at a common terminal of a logic element, an output of the first sub-circuit connected to the first dedicated logic terminal of the logic element, an output of the second sub-circuit connected to the second dedicated logic terminal of the logic element, and a circuit output at the common diffusion logic terminal of the logic element; and discontinuing the synthesis recursion cycle.

Preferably, extracting a first logic function, and a second logic function from a Shannon expansion of the synthesized function for a selected logic variable consists of: extracting the first logic function from the synthesized function by setting the selected variable to a logic high in the synthesized function; and extracting the second logic function from the synthesized function by setting the selected variable to a logic low in the synthesized function.

Preferably, the method contains the further step of adding a buffer to the circuit design to provide stabilization for a logic signal.

Preferably, the method contains the further step of adding an inverter to the circuit design to provide stabilization for a logic signal.

According to a fifth aspect of the present invention there is provided a method for providing a logic circuit. Each of the logic elements contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a p-type transistor having an outer diffusion connection, a gate connection, and an inner diffusion connection, and an n-type transistor having an outer diffusion connection, a gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor is connected to the first dedicated logic terminal, and the gate connection of the p-type transistor is connected to the first logic input. The outer diffusion connection of the n-type transistor is connected to the second dedicated logic terminal, and the gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type and the n-type transistors are connected together to form a common diffusion logic terminal. First a logic circuit design is obtained by setting a synthesized function equal to the required logic function, and performing a synthesis recursion cycle. The synthesis recursion cycle consists of the following steps: if the synthesized function comprises a single non-inverted logic variable, providing a logic circuit design comprising an input terminal for the non-inverted logic variable and discontinuing the synthesis recursion cycle; if the synthesized function comprises a high logic signal, providing a logic circuit design comprising a connection to a high logic level, and discontinuing the synthesis recursion cycle; if the synthesized function comprises a low logic signal, providing a logic circuit design comprising a connection to a low logic level, and discontinuing the synthesis recursion cycle; and if the synthesized function comprises either an inverted single variable or a multi-variable function, performing the following sequence of steps. The sequence of steps is: extracting a first logic function, and a second logic function from a Shannon expansion of the synthesized function for a selected logic variable; setting the synthesized function to the first logic function; performing a synthesis recursion cycle to obtain a circuit design for a first sub-circuit; setting the synthesized function to the second logic function; performing a synthesis recursion cycle to obtain a circuit design for a second sub-circuit; providing a logic circuit design comprising a logic element having an input terminal for the selected logic variable at a common terminal of a logic element, an output of the first sub-circuit connected to the first dedicated logic terminal of the logic element, an output of the second sub-circuit connected to the second dedicated logic terminal of the logic element, and a circuit output at the common diffusion logic terminal of the logic element; and discontinuing the synthesis recursion cycle. After obtaining the logic circuit design, the logic elements are connected in accordance with the obtained design.

Preferably, extracting a first logic function, and a second logic function from a Shannon expansion of the synthesized function for a selected logic variable consists of: extracting the first logic function from the synthesized function by setting the selected variable to a logic high in the synthesized function; and extracting the second logic function from the synthesized function by setting the selected variable to a logic low in the synthesized function.

Preferably, the method contains the further step of adding a buffer to the circuit design to provide stabilization for a logic signal.

Preferably, the method contains the further step of adding an inverter to the circuit design to provide stabilization for a logic signal.

The present invention successfully addresses the shortcomings of the presently known configurations by providing a fast and versatile logic circuit, with reduced area and power requirements, and capable of implementing a wide variety of logic functions.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, suitable methods and materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting.

Implementation of the method and system of the present invention involves performing or completing selected tasks or steps manually, automatically, or a combination thereof. Moreover, according to actual instrumentation and equipment of preferred embodiments of the method and system of the present invention, several selected steps could be implemented by hardware or by software on any operating system of any firmware or a combination thereof. For example, as hardware, selected steps of the invention could be implemented as a chip or a circuit. As software, selected steps of the invention could be implemented as a plurality of software instructions being executed by a computer using any suitable operating system. In any case, selected steps of the method and system of the invention could be described as being performed by a data processor, such as a computing platform for executing a plurality of instructions.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

The invention is herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice.

In the drawings:

FIG. 1 is a simplified block diagram of a logic circuit, according to a preferred embodiment of the present invention.

FIG. 2 is a simplified circuit diagram of a Gate Diffusion Input (GDI) logic cell, according to a preferred embodiment of the present invention.

FIG. 3 is a GDI circuit diagram and transient response when a step signal is applied to the outer diffusion node of an NMOS transistor, according to a preferred embodiment of the present invention.

FIG. 4 shows Cadence Spectre simulation results for sub-threshold operation of a GDI AND gate designed according to a preferred embodiment of the present invention.

FIG. 5 is a representation of a GDI cascade circuit designed in accordance with the present invention as an RC tree.

FIG. 6 is a circuit diagram of a GDI inverter along with its equivalent digital model, according to a preferred embodiment of the present invention.

FIG. 7 is a circuit diagram of a prior-art CMOS NAND gate, along with its equivalent digital model.

FIG. 8 is a simplified circuit diagram of a logic cell having separate common logic terminals, according to a preferred embodiment of the present invention.

FIG. 9 is a simplified circuit diagram of a latch based upon the GDI* cell, according to a preferred embodiment of the present invention.

FIGS. 10a-10e are simplified circuit diagrams of GDI based latches, according to a preferred embodiment of the present invention.

FIG. 11 is a simplified block diagram of a multi-transistor GDI logic circuit, according to a preferred embodiment of the present invention.

FIG. 12 shows a 3-input CMOS structure and the corresponding 5-input GDI cell.

FIG. 13 is a simplified block diagram of an extended GDI cell, according to a preferred embodiment of the present invention.

FIG. 14 is a simplified flowchart of a recursive algorithm for implementing any logic function by GDI cells, according to a preferred embodiment of the present invention.

FIG. 15 is a simplified flowchart of a method for designing a logic circuit, according to a preferred embodiment of the present invention.

FIG. 16 is a simplified flowchart of a method for extracting the first and second logic functions from a given function, according to a preferred embodiment of the present invention.

FIG. 17 is a simplified flowchart of a method for providing a GDI logic circuit, according to a preferred embodiment of the present invention.

FIGS. 18a, 18b, and 18c show GDI XOR, AND, and OR gates respectively, according to a preferred embodiment of the present invention, and their prior-art equivalents in CMOS, TG, and NMOS Pass-Gate (N-PG) technologies.

FIGS. 19a-19f shows power and delay results for GDI OR and AND gates according to a preferred embodiment of the present invention, and for prior-art CMOS, and PTL gates.

FIGS. 20a-20f shows implemented GDI cells and cell layouts for basic functions for a regular p-well process, according to a preferred embodiment of the present invention.

FIG. 21 shows generic prior-art carry-lookahead adders.

FIG. 22 shows a prior-art four-bit ripple comparator consisting of a cascade of 4 identical basic units.

FIG. 23 shows the structure of a prior-art 4-bit multiplier.

FIG. 24 shows a prior-art basic multiplier cell.

FIG. 25 shows layouts for 8-bit CLA adder circuits, according to a preferred embodiment of the present invention, and prior-art TG and CMOS circuits.

FIG. 26 shows simulation results for a GDI 8-bit adder designed according to a preferred embodiment of the present invention vs. prior-art CMOS and TG.

FIG. 27 shows a layout of an 8-bit comparator chip designed according to the present invention.

FIG. 28 shows simulation results for an 8-bit comparator, designed according to a preferred embodiment of the present invention.

FIG. 29 shows power, results as function of a for a 4-bit comparator, designed according to a preferred embodiment of the present invention.

FIG. 30 shows delay results as function of a for a 4-bit comparator, designed according to a preferred embodiment of the present invention.

FIG. 31 shows power-delay results as function of a for a 4-bit comparator, designed according to a preferred embodiment of the present invention.

FIG. 32 is a photograph of a test chip constructed in accordance with the present invention.

FIGS. 33a-33e shows five prior-art CMOS C-element circuits.

FIGS. 34a-34c shows three GDI implementations of the C-element, according to a preferred embodiment of the present invention.

FIGS. 35a and 35b show implementations of a three-input C-element for prior-art CMOS and GDI architectures respectively, according to a preferred embodiment of the present invention.

FIG. 36 shows a prior-art representation of a C-element by an SR-latch.

FIGS. 37a, 37b shows GDI SR-latch circuits, according to preferred embodiments of the present invention.

FIG. 38 shows the prior-art Muller pipeline structure.

FIG. 39 shows a GDI implementation of a dynamic C-element with inverted input, according to a preferred embodiment of the present invention.

FIG. 40 shows the simulation environment for a C-element, designed according to a preferred embodiment of the present invention.

FIG. 41 shows the simulation results for prior-art and GDI C-elements, according to preferred embodiments of the present invention.

FIG. 42 shows prior-art filter structure and the STG flow for a Bundled-Data Filter Controller.

FIGS. 43a and 43b show prior-art implementations of a Bundled-Data Filter Controller.

FIG. 44 shows simulation results for GDI and CMOS Bundled-Data Filter Controller, designed according to a preferred embodiment of the present invention.

FIG. 45 shows the general structure of a prior-art DR-ST implementation of a qDI combinational logic circuit.

FIG. 46 shows prior-art CMOS and GDI implementations of the ORN subnet, designed according to a preferred embodiment of the present invention.

FIG. 47 shows prior-art CMOS and GDI implementations of the XOR DRN subnet, designed according to a preferred embodiment of the present invention.

FIGS. 48a-48c shows three simulated circuits based on different combinations of ORN and DRN subnets, designed according to a preferred embodiment of the present invention.

FIG. 49 shows simulation results for DR-ST XOR circuits designed according to a preferred embodiment of the present invention.

FIG. 50 shows circuit diagrams for ORN subnet Full Adders, designed according to a preferred embodiment of the present invention.

FIG. 51 shows prior-art logic diagrams for DRN subnet Full Adders.

FIG. 52 shows performance results for DR-ST Full Adders, designed according to a preferred embodiment of the present invention.

FIG. 53 is a circuit diagram of a GDI 1-to-2 Decoder, according to a preferred embodiment of the present invention.

The rapid development of digital applications has created a demand for faster logic circuits, having compact implementation and low power dissipation. Traditional CMOS methods, and other technologies, such as PTL, have been unable to satisfy this demand. The present invention is of a low area, power-efficient logic circuit design, referred to below as gate-diffusion input (GDI), which can be used to implement a wide variety of logic functions.

The principles and operation of a logic circuit according to the present invention may be better understood with reference to the drawings and accompanying descriptions.

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.

Reference is now made to FIG. 1, which is a simplified block diagram of a logic circuit according to a preferred embodiment of the present invention. The logic circuit, which uses a GDI design, is based upon two complementary transistor networks, which connect to the GDI circuit logic inputs and outputs, and implement the desired logic function. The relationship between the structures of the two transistor networks and the overall function of the GDI circuit is discussed below, for the general case and for specific transistor network configurations.

Logic circuit 100 contains P logic block 110, N logic block 120, first and second logic inputs, 130 and 140, and three logic terminals: first and second dedicated logic terminals, 150 and 160, and common diffusion logic terminal 170. The first and second dedicated logic terminals, 150 and 160, and the common diffusion logic terminal 170 can each serve as either a logic signal input terminal or a logic signal output terminal, depending upon the specific logic circuit implementation. The preferred embodiments and examples given below illustrate several logic circuit terminal configurations.

The P logic block 110 contains a network of p-type transistors 180 which are interconnected to implement a given logic function. The P logic block 110 has three logic connections: an outer diffusion connection 181 (at an outer diffusion node of one of the p-type transistors), a gate connection 182 (at the gate of one of the p-type transistors), and an inner diffusion connection 183 (at the second inner diffusion node of one of the p-type transistors). Outer diffusion connection 181 connects to the first dedicated logic terminal 150, and gate terminal 182 connects to the first logic input 130. The N logic block 120 contains a network of n-type transistors 190 which implement the complementary logic function, and is structured similarly to the P logic block 110. The inner diffusion nodes of the P and N logic blocks, 183 and 193, are connected together to form the common diffusion logic terminal 170.

The p-type and n-type transistors may be field effect transistors (FET), CMOS transistors (p-well, n-well, or twin-well), SOI transistors, SOS transistors, or the like. Note that the customary distinction between the source and drain of the transistor can not be made with the GDI structure, since for any given transistor the relative voltages between the transistor diffusion nodes changes depending upon the logic input and output voltages. This is in contrast with the standard complementary CMOS structure in which the source or drain is tied to a constant voltage. Thus, for GDI logic circuits one of the two transistor diffusion nodes (not the gate) is arbitrarily selected to serve for the inner diffusion connection, and the other to serve for the outer diffusion connection. Not all GDI cell topologies can be implemented in standard p-well or n-well CMOS technology, due to interference of bulk effects under certain input/output conditions. GDI logic circuits are therefore preferably implemented in either twin-well CMOS or silicon-on-insulator/silicon-on-sapphire (SOI/SOS) technologies, which do not suffer from these limitations.

In the preferred embodiment of the GDI logic circuit, the common logic terminals are connected together to form a common logic input 196. Thus a logic signal at the common logic input 196 is applied to both the P and N logic blocks, 110 and 120. In one configuration known as a double-gate-input GDI circuit (GDI*), the logic input terminals, 130 and 140, are not connected, and each logic block has an independent logic input. The GDI* circuit is discussed in greater detail below (see FIG. 8).

A dual-transistor embodiment of the GDI logic circuit is designated herein as the GDI logic cell. Reference is now made to FIG. 2, which is a simplified circuit diagram of a standard GDI logic cell, according to a preferred embodiment of the present invention. In the standard GDI logic cell 200, the p-type and n-type transistor networks each contain a single transistor, 210 and 220 respectively. The GDI cell has a common input terminal (G) 230 connected to the gates of both the NMOS and PMOS transistors, a first dedicated logic terminal (P) 240 at the outer diffusion node of the PMOS transistor, and a second dedicated logic terminal (N) 250 at the outer diffusion node of the NMOS transistor 220. The common diffusion logic terminal (D) 260 is connected to the inner diffusion nodes of both transistors. The first and second dedicated logic terminals, 240 and 250, and the common diffusion logic terminal 260 may be used as either input or output ports, depending on the circuit structure. FIG. 2 omits bulk connections, although such connections may be required for some transistor technologies, including CMOS. The circuit diagrams for the GDI logic circuits presented below have transistor bulk connections, and are therefore appropriate for technologies with four-terminal transistors (i.e. transistors having gate, drain, source and bulk terminals), such as twin-well CMOS and SOL Bulk connections may not be needed for some transistor technologies, such as floating bulk SOI.

Table 1 shows six logic functions which can be implemented with a single GDI logic cell. The most general case is the multiplexer (MUX), where logic signal A is applied to the common input 230. Signal A selects one of the dedicated logic terminals, 240 or 250, and the logic cell outputs the selected logic signal at the common diffusion logic terminal 260. Other configurations listed in the table implement OR, AND, and inverter logic gates. The logic cell also implements the F1 function (ĀB) and the F2 function (Ā+B). Both the F1 and F2 functions are complete logic families, which can be used to realize any possible logic function.

TABLE 1 N (1st P (2nd G dedicat.) dedicat.) (Cmn.) D Function Low B A ĀB F1 B High A Ā + B F2 High B A A + B OR B Low A AB AND C B A ĀB + AC MUX Low High A Ā NOT

Many of the logic circuits presented below are based on the F1 and F2 functions. The reasons for this are as follows. First, as mentioned, both F1 and F2 are complete logic families. Additionally, F1 is the only GDI function that can be used for higher level circuit design that can be realized in a standard n-well CMOS process. In the F1 function implementation, the bulks of all NMOS transistors are constantly and equally biased, since the N terminal (first dedicated logic terminal) is tied low for all logic input levels. In the other configurations listed in Table 1 the N terminal is either tied high (OR gate), or varies according to the logic input levels (F2, AND, and MUX). Similarly, F2 can be realized in p-well CMOS. Finally, when the N input is driven at a high logic level and the P input is at low logic level, the diodes between NMOS and PMOS bulks to the logic circuit output are directly polarized, and the two dedicated logic terminals are shorted together. Being driven in such a way causes static power dissipation and an output voltage Vout˜0.5VDD. Utilizing the OR, AND and MUX implementations, in standard CMOS with VBS=0 configuration, as building blocks for more complex logic circuits is therefore problematic. The polarization effect can be reduced if the design is performed in floating-bulk SOI technologies, in which case floating-bulk effects have to be considered.

The GDI cell 200 differs significantly from the standard CMOS inverter, which it resembles structurally. Dedicated logic inputs 240 and 250 serve as logic signal inputs, not for applying pull-up and pull-down voltages as in the CMOS case. By extending the complementary structure to a three input structure, a much more versatile logic cell is obtained. A simple change of the input configuration of the GDI cell 200 corresponds to different Boolean functions. Most of these functions are complex (6-12 transistors) in CMOS, as well as in standard PTL implementations, but require only 2 transistors as a GDI logic circuit. Additionally, the bulks of transistors 210 and 220 may be connected to dedicated logic terminals 240 and 250 respectively, so that the transistors 210 and 220 can be arbitrarily biased. This is in contrast with a CMOS inverter, which cannot be biased.

The GDI cell structure provides advantages over both CMOS and PTL logic circuits in design complexity, transistor count and power dissipation. An operational analysis of the GDI logic cell is now presented, in which GDI circuit transient behavior, swing restoration, and switching characteristics are analyzed.

One of the common problems of PTL design methods is the low swing of output signals because of the threshold drop across the single-channel pass transistors. In existing PTL techniques additional buffering circuitry is used to overcome this problem. The following analysis of the low swing performance of the GDI cell is based on the F1 function, and can be easily extended for other GDI functions. Table 2 presents a full set of logic states and the related functionality modes for the F1 function.

TABLE 2

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