Electrically conductive interconnect system and method   

Abstract: An electrically conductive interconnect system has a post, extending above a supporting surface, the post including a rigid material, a coating on the rigid material, wherein the post and has a first width at the supporting surface and a second width at a distance removed from the supporting surface, and the post narrows from the first width to the second width. A method of electrically connecting a portion of a first supporting surface to a portion of a second supporting surface involves bringing a post on the first supporting surface into contact with an electrically conductive material located on the second supporting surface, softening the electrically conductive material, causing a separation distance between the first supporting surface and the second supporting distance to decrease so that a portion of the post will be surrounded by the electrically conductive material, and allowing the temperature of the electrically conductive material to decrease.

The present application is a division of U.S. patent application Ser. No. 11/778,461, filed Jul. 16, 2007, which is a continuation of U.S. patent application Ser. No. 11/422,551, filed Jun. 6, 2006 (now U.S. Pat. No. 7,847,412), which claims priority to U.S. Provisional Patent Application No. 60/690,759, filed Jun. 14, 2005, each of which is herein incorporated by reference in its entirety.

The present application relates generally to the field of making electrical contacts that extend all the way through an electronic chip (by creating electrically conductive vias) is difficult. Doing so with precision or controlled repeatability, let alone in volume is nearly impossible unless one or more of the following is the case: a) the vias are very shallow, i.e. significantly less than 100 microns in depth, b) the via width is large, or c) the vias are separated by large distances, i.e. many times the via width. The difficulty is compounded when the vias are close enough for signal cross-talk to occur, or if the chip through which the via passes has a charge, because the conductor in the via can not be allowed act as a short, nor can it carry a charge different from the charge of the pertinent portion of the chip. In addition, conventional processes, to the extent they exist, are unsuitable for use with formed integrated circuit (IC) chips (i.e. containing active semiconductor devices) and increase cost because those processes can damage the chips and thereby reduce the ultimate yield. Adding further to the above difficulties is the need to be concerned with capacitance and resistance problems when the material the via passes through has a charge or when the frequencies of the signals to be carried through the vias are very high, for example, in excess of about 0.3 GHz.

Indeed, there are numerous problems that are extant in the semiconductor art including: use of large, non-scalable packaging; assembly costs don\'t scale like semiconductors; chip cost is proportional to area, and the highest performance processes are the most expensive, but only fraction of chip area actually requires high-performance processes; current processes are limited in voltage and other technologies; chip designers are limited to one process and one material for design; large, high power pad drivers are needed for chip-to-chip (through package) connections; even small changes or correction of trivial design errors require fabrication of one or more new masks for a whole new chip; making whole new chips requires millions of dollars in mask costs alone; individual chips are difficult and complicated to test and combinations of chips are even more difficult to test prior to complete packaging.

Accordingly, there is a significant need in the art for technology that can address one or more of the above problems.

SUMMARY

We have developed an electrically conductive interconnect system. One aspect of the interconnect system involves a post, extending above a supporting surface of a thickness. The post has a rigid material, a coating on the rigid material, and a first width at the supporting surface and a second width at a distance removed from the supporting surface. The post narrows from the first width to the second width as a spacing from the supporting surface increases to the distance. The system further has an electrically conductive path along a first surface of the supporting surface and coupled to the post.

Another aspect involves a method of electrically connecting a portion of a first supporting surface to a portion of a second supporting surface. The method involves bringing a post on the first supporting surface into contact with an electrically conductive material located on the second supporting surface, softening the electrically conductive material by causing the electrically conductive material to reach a temperature of between 240° C. and 270° C. causing a separation distance between the first supporting surface and the second supporting distance to decrease so that a portion of the post will be surrounded by the electrically conductive material, and allowing the temperature of the electrically conductive material to decrease so that, when cooled, an electrically conductive connection will exist extending from the portion of the first supporting surface, through the post and through the electrically conductive material to the portion of a second supporting surface.

The advantages and features described herein are a few of the many advantages and features available from representative embodiments and are presented only to assist in understanding the invention. It should be understood that they are not to be considered limitations on the invention as defined by the claims, or limitations on equivalents to the claims. For instance, some of these advantages are mutually contradictory, in that they cannot be simultaneously present in a single embodiment. Similarly, some advantages are applicable to one aspect of the invention, and inapplicable to others. Thus, this summary of features and advantages should not be considered dispositive in determining equivalence. Additional features and advantages of the invention will become apparent in the following description, from the drawings, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified representation a side view of a portion of a chip containing multiple active electronic devices;

FIG. 2 is a top view of the upper surface of the specified area of FIG. 1;

FIG. 3 shows a simplified cutaway view of the portion of FIG. 1;

FIG. 4 is a top view of the upper surface of the specified area of FIG. 1 following creation of the trench shown in side view in FIG. 3;

FIG. 5 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing;

FIG. 6 is a top view of the upper surface of the specified area of FIG. 1 following the filling of the trench with electrically insulating material shown in side view in FIG. 5;

FIG. 7 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing;

FIG. 8 is a top view of the upper surface of the specified area 124 of FIG. 1 following the creation of the via trench;

FIG. 9 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing;

FIG. 10 is a top view of the upper surface of the specified area of FIG. 1 following metallization of the via trench;

FIG. 11 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued optional processing;

FIG. 12 is a top view of the upper surface of the specified area of FIG. 1 following the optional introduction of the bonding substance into the remaining void;

FIG. 13 shows a simplified cutaway view of the portion of FIG. 1 as a result of other optional processing;

FIG. 14 is a top view of the upper surface of the specified area of FIG. 1 following the optional addition of the finishing substance into the remaining void;

FIG. 15 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing;

FIG. 16 shows a simplified cutaway view of the portion of FIG. 1 following thinning of the substrate to remove the bottom metallization;

FIG. 17 shows a simplified cutaway view of the portion of FIG. 5 as a result of processing of an alternative variant;

FIG. 18 is a top view of a section taken below the specified area of FIG. 1 following the creation of the via trench;

FIG. 19 shows a simplified cutaway view of the portion of FIG. 5 as a result of further processing in the manner described in connection with FIG. 9;

FIG. 20 shows a simplified cutaway view of the portion of FIG. 5 as a result of further optional processing in the manner described in connection with FIG. 11;

FIG. 21 shows a simplified cutaway view of the portion of FIG. 5 as a result of further optional processing in the manner described in connection with FIG. 13;

FIG. 22 shows a simplified cutaway view of the portion of FIG. 5 as a result of thinning the substrate to expose the bottom metallization in the manner described in connection with FIG. 15 in the alternative variant of FIG. 17;

FIG. 23 shows a simplified cutaway view of the portion of FIG. 5 as a result of thinning the substrate to remove the bottom metallization in the manner described in connection with FIG. 16 for the alternative variant of FIG. 17;

FIG. 24 illustrates in simplified form a dual conductor variant following metallization of the sidewalls;

FIG. 25 illustrates in simplified form the dual conductor variant following filling the trench with electrically insulating material 500;

FIG. 26 illustrates in simplified form, a via trench created by removing the entire island of semiconductor material;

FIG. 27 illustrates in simplified form, a via trench created by removing only an inner portion island of semiconductor material;

FIGS. 28A and 28B illustrate in simplified form one example dual-conductor variant;

FIGS. 29A and 29B illustrate in simplified form another example dual-conductor variant;

FIGS. 30A and 30B respectively illustrate use of an optional additional thermally created dielectric or insulator in the approaches of FIGS. 28 and 29;

FIG. 31 illustrates in simplified form one example three-conductor variant;

FIG. 32 shows a simplified cutaway view of a portion of an example alternative chip implementation similar to the implementation of FIG. 9 through FIG. 16 except the void remaining after metallization is not filled;

FIG. 33 shows a simplified cutaway view of a portion of an example alternative chip implementation, similar to that of FIG. 23 except the void remaining after metallization is not filled;

FIG. 34 and FIG. 35 each show the respective cross sections of the chips of FIG. 32 and FIG. 33 following hybridization to each other;

FIG. 36 shows the implementation of FIG. 34 after optional coating with an insulator or conformal coating;

FIG. 37 shows representative examples of cross sections of annulus trenches;

FIG. 38 illustrates in simplified form, a generic overview form a process for preparing a wafer for stacking;

FIGS. 39 through 41 illustrate portions of example chips processed to create through-chip connections using different variants of the herein-described processes that have, thereafter, been stacked together to form a chip unit;

FIG. 42 illustrates in simplified form the process for making a back to front variant;

FIG. 43 illustrates in simplified form the process for making a capacitive coupling variant;

FIG. 44 illustrates in simplified form the process for making a pre-connect variant;

FIGS. 45 and 46 illustrate in simplified form, example tack and fuse parameters;

FIG. 47 is a simplified example involving “minimal” contacts;

FIG. 48 is a simplified example involving an extended contact;

FIG. 49 illustrates a portion of a stack of semiconductor chips each having through-chip connections as described herein;

FIG. 50 illustrates a portion of the simplified stack of the chips shown in FIG. 49 stacked using a the post and penetration connection approach;

FIG. 51 illustrates in simplified form a void within the metallization filled by a pre-formed post;

FIG. 52 illustrates, in simplified form, the chip of FIG. 51 after it has been hybridized to an electronic chip;

FIG. 53 through FIG. 71 illustrate a simplified example variant of a basic contact formation and hybridization approach;

FIG. 72 through FIG. 87 illustrate an alternative simplified example variant of a basic contact formation and hybridization approach;

FIG. 88 through FIG. 91 illustrate, in simplified parallel form, a first part of two further example variant approaches for forming what will later become a rigid post on the back side of a daughter wafer;

FIG. 92 is a cross sectional photograph of example sloping vias;

FIG. 93 is a photograph of an example via having a depth of 100 microns and a diameter of 20 microns;

FIG. 94 is a photograph, in cross section, of a chip having pointed vias formed therein;

FIG. 95 through FIG. 102 illustrate, in simplified parallel form, a second part of the two further example variant from FIGS. 88 through 91;

FIG. 103 through FIG. 125 illustrate, in simplified parallel form, a variant process of preparing wafers for hybridization to other elements;

FIG. 126 through FIG. 139 illustrate in abbreviated form, a further variant process of preparing wafers for hybridization to other elements;

FIG. 140 which illustrates, in simplified form, a daughter wafer contact and a mother wafer contact immediately prior to the tack phase;

FIG. 141 shows, in simplified form, the contacts of FIG. 140 after the fuse process is complete;

FIG. 142 illustrates a profiled malleable contact;

FIGS. 143A through 143Y are representative, illustrative examples of some of the myriad of possible mother contact profiles;

FIG. 144 is a photograph of an alternative example profiled malleable contact;

FIG. 145 is a photograph of a profiled rigid contact designed to penetrate the malleable contact of FIG. 144;

FIG. 146 illustrates, in simplified form, a further profiled contact example;

FIGS. 147 through 152 illustrate one variant process for implementing the well attach concept;

FIGS. 153 through 156 illustrate, in simplified form, classes of reverse well variants;

FIGS. 157A and 157B are, respectively, photographs in longitudinal cross section of a set of 15 micron diameter vias extending 135 microns deep and 25 micron diameter vias extending 155 microns deep;

FIG. 158, is a photograph of a via similar to those of FIGS. 157A and 157B but not filled all of the way to the bottom;

FIGS. 159 through 167 illustrate a further variant of a Class II-type rigid well attach approach;

FIG. 168 through FIG. 170 show a further variant of the well attach approach in which the chips are attached to one another by separate remote contacts;

FIGS. 171A and 171B illustrate top views of alternative remote contact variants;

FIG. 172 illustrates cross sections of example coaxial contacts;

FIGS. 173 through 175 illustrate example uses of coaxial contacts;

FIGS. 176 through 179 illustrate two simple examples of hermetic sealing using contacts as described herein;

FIG. 180 is a chart summarizing different approaches for forming other variants using the rigid/malleable contact paradigm;

FIGS. 181A, 181B and 182 are charts summarizing different approaches for forming via variants;

FIGS. 183 through 195 illustrate in greater detail the process flow for a particular instance involving deposition of metal on a daughter wafer;

FIGS. 196 through 205 illustrate in greater detail the process flow for a particular instance involving plating of metal on a daughter wafer;

FIGS. 206a-c illustrate in simplified form a mother wafer electroless plating variant;

FIGS. 207a-e illustrate in simplified form a mother wafer thin dielectric variant;

FIGS. 208a-e illustrates in simplified form a mother wafer thick dielectric variant;

FIG. 209 illustrates an example and some typical dimensions for a mother wafer contact, having 14 micron wide contact pads spaced on a 50 micron pitch, before barrier deposition;

FIG. 210 illustrates the contact of FIG. 209 after barrier and cap deposition;

FIG. 211 illustrates typical dimensions for a mother wafer contact, having 8 micron wide contact pads spaced on a 25 micron pitch;

FIG. 212 illustrates an example and some typical dimensions for a daughter wafer contact having 14 micron wide contact pads spaced on a 50 micron pitch, created by deposition;

FIG. 213 illustrates an example and some typical dimensions for a daughter wafer contact having 8 micron wide contact pads spaced on a 25 micron pitch, created by deposition;

FIG. 214 illustrates an example and some typical dimensions for a plated version mother wafer contact, having 14 micron wide contact pads spaced on a 50 micron pitch before a self aligned seed etch is performed;

FIG. 215 illustrates the contact of FIG. 214 after the self aligned seed etch is performed;

FIG. 216 illustrates using the inner via as part of a heat pipe arrangement;

FIG. 217 illustrates in simplified parallel form an example isolation and spanning variant;

FIG. 218 illustrates in simplified parallel form another example isolation and spanning variant;

FIG. 219 illustrates in simplified form a representative example conventional microprocessor chip and its respective constituent elements;

FIGS. 220A-D illustrate in simplified form how an alternative microprocessor can be constructed from the elements of the microprocessor of FIG. 219 to provide a smaller footprint and substantially reduced distances between elements;

FIG. 221 shows a direct comparison of the footprint of the chip of FIG. 219 to that of the chip of FIGS. 220 A-D;

FIG. 222 illustrates functional packaging variants;

FIG. 223 illustrates details for variants of the packaging of FIG. 222;

FIGS. 224 through 231 illustrate in simplified overview a routing less processing variant;

FIGS. 232 through 235 illustrate in simplified form alternative routing less variants;

FIG. 236 illustrates in simplified form the use of an optical, rather than wired, connection between two chips;

FIG. 237 illustrates in simplified form use of a variant of the heat pipe configuration to allow light to pass from a laser-bearing chip to a photo detector-bearing chip even though there are two other chips interposed between them;

FIG. 238 illustrates in simplified form the tack and fuse process approach;

FIG. 239 illustrates in simplified form the functional layers of a daughter contact;

FIG. 240 illustrates in simplified form the functional layers of a mother contact;

FIG. 241 in simplified form example material configurations of the functional layers of daughter contacts;

FIG. 242 in simplified form example material configurations of the functional layers of mother contacts;

FIGS. 243A, 243B and 243C are photographs of joined mother and daughter contacts;

FIGS. 244 and 245 illustrate in simplified form single pin-per-chip tooling;

FIGS. 246 and 247 illustrate in simplified form multiple pins-per-chip tooling;

FIGS. 248 and 249 illustrate in simplified form an alternative tooling approach; and

FIGS. 250 through 254 illustrate in simplified form another alternative tooling approach.

DETAILED DESCRIPTION

At the outset, it is to be understood that the term “wafer” as used herein is intended to interchangeably encompass all of the terms “chip,” “die” and “wafer” unless the specific statement is clearly and exclusively only referring to an entire wafer from which chips can be diced, for example, in references to an 8 inch or 12 inch wafer, chip or die “-to-wafer”, “wafer-to-wafer”, or “wafer scale” processing. If use of the term would, as a technical matter, make sense if replaced by the term “chip” or “die”, those terms are also intended. Moreover, a substantive reference to “wafer or chip” or “wafer or die” herein should be considered an inadvertent redundancy unless the above is satisfied.

In general, specific implementations of aspects described herein make it possible to form connections among two or more wafers containing fully-formed electronic, active optical or electro-optical devices in a simple, controllable fashion which also allows for a deep via depth, high repeatability, controlled capacitance and resistance, and electrical isolation between the via and the wafer or substrate through which the via passes.

Implementations of our process make it possible to form an electrically conductive via that is narrow in width (i.e. down to about 15 microns wide or less) as well as deep (i.e. to more than about 50 microns in depth) through a chip of depth to width ratios on the order of 3:1 and as much as 30:1, although aspect rations on the order of 5:1 to 10:1 will be more typical. Moreover, our approach advantageously makes it possible to do so in circumstances where the portion of the chip the via passes through will be electrically active. Specifically, we make it possible to provide electrical access through the doped semiconductor part of a wafer using a passage where side-walls insulate the doped semiconductor from an electrical conductor which propagates through the passage. Moreover, our process works for narrow passages (i.e. about 15 microns wide or, in some cases less) while allowing for tight control of the thickness of the isolating material and the electrical conductor so as to maintain a constant and acceptable capacitance and resistance.

Still further, our approach is suitable for use in forming contacts having, if circular, a diameter of between 0.1 micron to 15 micron pads, the upper end not being a limit but rather simply the size below which our approach permits integration not generally possible with other approaches, and the lower end being a function of currently available photolithography technology. In other words, advances in photolithographic technology that allow for smaller definition will also allow the current limit to go smaller.

Still further, and unlike solder contacts, which can be hundreds or thousands of microns long, or wirebond contacts, which can also be thousands of microns long and thus often require significant pad drivers to drive the impedance between chips, through our approaches, we can use very short contacts (10 microns or less) which allows much lower parasitic electrical effects between the chips. Our typical contact has spacing between contacts three times or less the width of the malleable material (defined and discussed below) prior to integration with a complementary contact (e.g. if the initial contact is 8 microns high, spacing between contacts would be up to about 25 microns.

Our approach further permits stacking of chips on a separation spacing of less than or equal to about 20 microns. In practice, less than or equal to 10 micron spacing will be typical, although we have demonstrated that less than about 1 micron spacing can be done. In general, the minimum is determined by the topology of the closest surfaces of the two wafers being joined; when they are touching at their highest points the distance between the pads represents the maximum height spacing.

Our approach further makes it possible to form contacts on a pitch of less than or equal to 50 microns. Typically, pitches of less that or equal to about 25 microns will be used, although we have demonstrated that pitches as small as 7 microns can be done, again that limit being a function of currently available photolithography technology. Here too, as technology advances, pitches can be smaller.

Features of some variants include one or more of the following: potential for millions of contacts/cm2; electrical, mechanical and thermal attachment occurs concurrently; attachment done with low force but yields high strength connection (on the order of 1,000 kg/cm2); connections can be done with economies of scale; non-planar wafers can be accommodated; most processing can be done on a wafer scale (e.g. 10 micron GaAs on 8″, 10″ or 12″ wafers); processes can be done on a chip to chip, chip to wafer, or wafer to wafer basis; processes are electrically grounded; connections are made on a pre-formed (i.e. device bearing chip) so can be used with third-party supplied chips; making of vias before multiple chips are connected; capability to test chip combination before it is permanently connected and to rework if necessary; mixing and matching of different technologies (i.e. GaAs to InP, InP to Si, GaAs to Si, SiGe to SiGe to Si, etc. and even an insulator wafer made of, for example, ceramic, LCP or glass); an ability to create chip-sized packages that take advantage of semiconductor process economies; ability to allow low-speed functions to be moved off of core, expensive processes, but still have entire set of circuits act like a single chip, allows design of an individual chip to take advantage of the variety of voltages, technologies, and materials available and best suited for that particular design; irrespective of the technologies required for other aspects of the design; enhanced off-chip communication; facilitates increased modularity of design at the chip level allowing leverage of core designs into multiple products without having to absorb redundant non-recurring engineering costs; and allows matching of speed with technology type so that low speed circuitry need not be formed on expensive, higher speed technology than necessary.

In overview, our processes improve the ability to create a chip-to-chip connection using “through-wafer” electrical contact that can be used with a doped substrate but will not short out the substrate and thus can carry an opposite charge to that of the substrate through which it passes. In addition, this “through-wafer” approach is usable with wafers of semiconductor materials, insulators such as ceramics, and other conductive or non-conductive materials. Moreover, using current equipment for etching semiconductor materials, i.e. having a 30 to 1 aspect ratio, the process works well for vias of narrow cross section (i.e. 15 microns wide, or in some cases less) and vias extending for an overall depth from in excess of 50 microns to depths of 500 microns or more. In addition, the process allows for close control of capacitance and resistance such that, for example, the vias created using the process can carry high speed electrical signals (i.e. of frequencies in excess of 0.3 GHz) or, in some implementations, optical signals.

Some implementations will also allow for concentric vias that, if conductive, can each carry different signals or different charges. Still further, some implementations allow for concentric vias in which the inner via can be used to as part of a cooling system by using a part of the arrangement to become part of a heat pipe arrangement. Other implementations provide the advantage that they are compatible with, and allow use of, stacking approaches in which chips are stacked and electrically connected to other chips on a chip-to-chip, chip-to-wafer or wafer-to-wafer basis.

Advantageously, virtually all of the stacking processes and variants described herein, or straightforwardly derived therefrom, only require a new stacked piece to be aligned to the piece directly below it. This is in sharp contrast to prior art techniques that attempted to stack and which must align all pieces in the stack together and then insert a conductive material to form the trans-stack connections. Such an approach requires all of the pieces in the stack to be accurately aligned with respect to every other piece in common rather than just to the piece below it. Moreover, our approaches work equally well with uniaxial, coaxial and triaxial connections, whereas alignment in-common approaches do not, if they can be done at all.

The various approaches are described for simplicity by way of example, using examples involving wafers of semiconductor material, for example silicon (Si), silicon-germanium (SiGe), gallium-arsenide (GaAs), etc., that have been pre-formed (i.e. they already contain integrated circuits or their components, and/or optical devices such as lasers, detectors, modulators as well as contact pads for those devices).

The first example of the approach involves a two-etch process where only wafer, for purposes of example semiconductor material (i.e. doped semiconductor with or without some or all of its associated substrate), needs to be etched. This example process begins with a device-bearing wafer of semiconductor material. One or more trench regions of precise width are etched in the wafer to the desired depth such that, in the case of a semiconductor wafer, the trench extends into the wafer substrate and creates a perimeter about a portion of the semiconductor material. Notably, the shape of the perimeter can be any closed shape and the outer and inner walls of the trench need not be the same shape. Capacitance and resistance of the ultimate via connection can be controlled through selection of the shape of the inner and outer perimeter of the trench and their separation distance(s). The trench depth is typically 50 microns or more, in some cases 500 microns or more, but the trench does not propagate through the entire substrate of the wafer so that the bounded semiconductor piece doesn\'t fall out. The trench is then filled with an electrically insulating material. At least a portion of the bounded semiconductor piece is then etched away leaving a hole of narrower cross section than that bounded by the outer trench wall, such that the via created by etching the semiconductor piece is bounded either by insulating material or a perimeter ring of material from the center semiconductor piece for part of its depth and substrate for the rest. The hole is metalized to create an electrical connection between the top of the wafer and the bottom of the hole. The back of the wafer (i.e. the substrate) is then thinned to expose metallization at the bottom of the hole which then becomes a substrate side contact or a portion thereof (interchangeably referred to herein by the broad term “contact”). Typically, at least the full depth of a portion of the surface defining the hole will be metalized, although in some implementations the metallization will only extend to a sufficient depth that it will be exposed when the substrate is sufficiently thinned. In this manner, if the process used to perform the metallization can not be used to metalize down to the full depth, as long as sufficient metallization extends down to where the thinning will stop, the contact can be formed. For example, in one example implementation, if the via extends partway into the substrate for a total length of about 600 microns, but the metallization can only be reliably done to an overall depth of about 300 microns (i.e. 300 microns less than the via itself), the process is not adversely affected so long as the substrate can be thinned to at least reach the metallization without unacceptably weakening the wafer or chip.

Through the above approach, variants described herein, and permutations and combinations thereof, connection points can be brought closer to the on-chip devices. By bringing connection points closer to on-chip devices, this approach facilitates chip-to-chip connections in the vertical direction (i.e. through chip stacking), can reduce the distance between connection points, and reduce or eliminate the need to use wirebonds for chip to chip connections. Moreover, the approach facilitates creation of sub-component specialty designs that can be mixed and matched as desired during production. In other words, a third dimension becomes more readily available for chipset materials, geometries and manufacture. In addition, the approach enables mixing of different speed or types of material technologies as well as mix-and-matching of component or subcomponent designs thereby providing development and manufacturing cost savings. Still further chip-to-chip connections can be created that use optical rather than electrical connections between chips.

The above is further facilitated through the optional use of a chip-to-chip connection approach that reduces the stress on chips being joined, thereby reducing the risk of chip damage.

The particular aspects described above are illustrated in greater detail by way of a number of examples and with specific reference to figures which, for purposes of illustration and clarity of presentation, are overly simplified and not to scale. In some cases, the scales are intentionally grossly exaggerated or distorted at the expense of accuracy for enhanced clarity of presentation and understanding.

Moreover, the approaches described herein are independent of the particular devices on the chip or with which the aspects described herein are used. Thus, the references to any specific type of device, for example the laser of the first example, are arbitrary and irrelevant to the aspects described herein except to the extent that they are devices to which electrical contact may need to be made. In other words, the approaches described herein are essentially identical for all devices and circuit elements to which contact may be made.

FIG. 1 is a simplified side view of a portion 100 of a chip 102 containing multiple solid state electronic devices, for example, resistors, capacitors, transistors, diodes, lasers, photodetectors or some combination thereof. The portion 100 shown in FIG. 1, for example purposes only, comprises a laser 104, having a “top” mirror 106 an active region 108 below the top mirror 106 and a “bottom” mirror 110, located on a substrate 112, such that the device 104 has a height 114 several microns above the top outer surface 116 of the non-device portion of the chip 102 near the device 104.

As shown, the laser 104 is a conventional vertical cavity surface emitting laser (VCSEL). For purposes of explanation, it should be assumed that the top mirror 106 will need to be electrically connected to some element on the side 118 of the substrate opposite the side 120 carrying the laser 104 and pass through the doped semiconductor material 122 near the device 104 within a specified area 124.

At the outset, it should be understood that to the extend lasers or photodetectors are discussed as the devices, the terms “top” and “bottom” follow a convention whereby the “bottom” is the portion closest to the substrate, irrespective of whether the laser emits towards or away from the substrate 112 (or in the case of a photodetector the direction from which it receives light).

FIG. 2 is a top view of the upper surface 116 of the specified area 124 of FIG. 1 before the process starts.

The basic process of forming the through-chip contact will be described with reference to those aspects introduced in FIGS. 1 and 2.

FIG. 3 shows a simplified cutaway view of the portion 100 of FIG. 1 as a result of processing as follows.

First, a trench 302 is etched into and through the semiconductor material 122, preferably using an anisotropic etching process (in order to create relatively straight trench sidewalls 304), to a depth that brings the trench 302 part way into the substrate 112. The overall depth of the trench 302 can be 100 microns or more, in some cases extending for 500 to 600 microns or more. However, the trench 302 should stop before extending completely through the substrate 112 otherwise the ability to implement the invention can, in many cases, be lost. The trench 302 is shaped such that it is closed on itself creating a cross section in a plane parallel to the plane of the substrate that is an annulus. Through use of this annular trench 302, an “island” 306 of the semiconductor material 122 will remain and be held in place at least by the intact part 308 of the substrate 112. At this point it is worth noting that, while the “annulus” referred to for the trench 302 is shown as circular in shape, this is only for purposes of simplicity of illustration. As used herein, the terms “annular” or “annulus” should be understood to not be limited to any particular or regular shape nor does the outer periphery have to have the same shape as the inner periphery. As long as the trench is a closed shape so that it creates an isolated “island” within it, the trench is to be considered an annulus trench or “annular” as used herein. In other words, the terms are intended to include any combination of closed perimeter shapes including closed polygons (regular or irregular) or other closed perimeter shapes whether, for example, the shape is smooth, erose, etc. Moreover, the terms are intended to encompass fixed and varying widths as needed or desired for the particular instance.

FIG. 4 is a top view of the upper surface 116 of the specified area 124 of FIG. 1 following creation of the trench 302 shown in side view in FIG. 3. In this view, the annulus nature of the trench 302 is clearly visible. The trench 302 has a closed inner 312 and outer 314 perimeter and a width 310 so that the trench 302 surrounds, and thereby creates, an island 306 from the semiconductor material 122 within it.

FIG. 5 shows a simplified cutaway view of the portion 100 of FIG. 1 as a result of continued processing as follows.

At least the trench 302 is coated with a dielectric or other electrically insulating material 500, which can optionally also cover a portion of the top outer surface 116 to a desired thickness. Optionally, if heat transfer is a concern a material that, while electrically insulating, is a good thermal conductor may be used as the electrically insulating material 500.

Advantages achieved by the above approach can be appreciated when viewed in contrast in the context of the prior art. First, as a general matter, it is extremely difficult to apply dielectric materials in a uniform manner, particularly where a uniform thickness is required. Second, this problem is compounded when the dielectric needs to be applied to a non-flat surface and is further compounded when they must be applied to vertical walls, such as those of the vias described herein. Thus, to the extent other approaches attempt to create holes and then accurately coat the walls of those holes with dielectric and thereafter make them conductive, those approaches lack any meaningful ability to control uniformity. The lack of uniformity present in those approaches dramatically affects capacitance and impedance, and hence performance, particularly where the signal frequencies involved will be very high, for example, in excess of about 0.3 GHz. In contrast, with the approaches described herein, precise control of capacitance and resistance is possible because the dimensions of the trench 302 can be precisely controlled to the precision of the trench 302 itself. The peripheral walls of the trench 302 define the thickness and uniformity in coverage of the insulating material 500 (and hence, the ultimate capacitance and impedance) because they constrain it. Therefore, all that is required is ensuring that the trench 302 is filled—a very low precision and low cost process. Thus, unlike the prior art, precision during application of the dielectric is unnecessary.

FIG. 6 is a top view of the upper surface 116 of the specified area 124 of FIG. 1 as shown in side view in FIG. 5, following the filling of the trench 302 and (optional) partially also covering some of the top outer surface 116 with the electrically insulating material 500.

FIG. 7 shows a simplified cutaway view of the portion 100 of FIG. 1 as a result of continued processing as follows.

Once the electrically insulating material 500 has solidified (by hardening, curing or other processing), a via trench 702 is created by removing the island 306 of semiconductor material within the annulus 704 of insulating material 500 to a sufficient depth 502 necessary to achieve the particular desired implementation, for purposes of example, a depth similar in depth to that of the trench 302 (i.e. such that it too extends some distance into the substrate 112 but preferably not fully through it). In practice, the depth 502 of the via trench 702 can be longer or shorter than depth of the trench 302 provided it too extends sufficiently deep that it can be reached, if necessary during processing as described below, in this example case, essentially the same distance into the substrate 112 as the trench 302. Moreover, the innermost wall of the annulus 704 that bounds the island 306 dictates the shape and profile of the via trench 702 that is created by the removal process will be a dielectric. Accordingly, it will not typically be impacted by an etch process, a low precision etch process can be used to remove the island 306 of semiconductor material because rigorous control of the removal is unnecessary in the width or depth directions. Of course, removal can be augmented, or alternatively otherwise be accomplished, by using one or more other suitable processes, for example, laser ablation, laser drilling or some combination thereof.

Continuing with the process of this example, once the via trench 702 has been created, the sidewall(s) 706 of the via trench 702, as well as the bottom 708 of the via trench 702, will all be electrically non-conducting because the sidewall(s) 706 will be the insulating material 500 and the bottom 708 will be defined by the substrate 112.

FIG. 8 is a top view of the upper surface 116 of the specified area 124 of FIG. 1 following the creation of the via trench 702 within the annulus 704 of electrically insulating material 500 shown in side view in FIG. 7.

FIG. 9 shows a simplified cutaway view of the portion 100 of FIG. 1 as a result of continued processing as follows.

The via trench 702 is made electrically conductive by “metalizing” at least a longitudinal portion of the via trench sidewall surface 706 (i.e. along its depth), for example, using sputtering, evaporation, plating or other physical or chemical deposition techniques for applying metals or, if need be, some combination thereof. In other words, the metalizing can involve use of a conductive solid, conductive epoxy or reflowable material (e.g. an appropriate temperature conductive liquidus like a solder). This metalizing process can, and typically will, be used to create a continuous electrically conductive connection from at least about the via bottom 708 to the upper surface 116, and in many cases, all the way to the device of interest if it is part of the chip in which the via was made. By way of representative example FIG. 9 shows an electrical trace 902 created by this process extending from a contact 904 on the upper mirror 106 of the laser 104 to the bottom 708 of the via trench 702. As shown, the entire surfaces of the sidewall(s) 706 and bottom 708 of the via trench 702 are completely coated with metal.

As noted above, because the width and length of the insulating annulus can be rigorously controlled, as can the thickness of the conductor formed by the metalizing, a constant capacitance relative to the metalized surface can be achieved. Moreover, the insulating material 500 electrically isolates the contact 904 from the semiconductor material 122 it is passing through and thus, can account for defects in the semiconductor material that might otherwise electrically short the contact to another device or conductor.

FIG. 10 is a top view of the upper surface 116 of the specified area 124 of FIG. 1 following metallization of the via trench 702 and creation of the electrical trace 902 to the device contact 904 as shown in side view in FIG. 9.

FIG. 11 through FIG. 14 illustrate additional, optional, processing that may be useful or desirable for some implementations. The approach shown in FIG. 11 or FIG. 12 is independent of the approach shown in FIG. 13 or FIG. 14. As a result, depending upon the particular implementation, either the approach shown in FIG. 11 and FIG. 12 or the approach shown in FIG. 13 and FIG. 14 can be separately used, or the two approaches can be used together in either order.

There are several advantages that can be obtained through use of one or both of these optional approaches. First, filling the void with a material adds mechanical strength and increases structural rigidity thereby reducing potential stresses. Second, the use of solder, an epoxy or other bonding material can aid in the ultimate connection of the chip to another element, particularly when the connection involves hybridization of that chip to another chip. Third, by inserting a material into the void, the risk of undesirable materials entering the void is reduced. Finally, the filler material reduces or eliminates the possibility of damaging the metalized portion within the via trench, particularly if less than the total sidewall is metalized. In addition, by varying the thickness of the insulator and metal, the coefficient of thermal expansion (“CTE”) of the wafer can be balanced so as to match that of the wafer. For example, an oxide (CTE of 1 ppm) can be used in conjunction with copper (CTE of 17 ppm) to match the CTE of silicon (CTE of 2.5 ppm).

Of course, since these aspects are both optional, both can be dispensed with while still using the invention. For completeness of understanding however, both processes are illustrated in connection with FIG. 11 through FIG. 14.

FIG. 11 shows a simplified cutaway view of the portion 100 of FIG. 1 as a result of the optional processing as follows.

Once the metallization is complete, if the remaining void 1100 is not going to be left empty for use as described later, the remaining void 1100 can optionally be partially or wholly filled with some material, for example, in this case a bonding substance 1102. Depending upon the particular implementation this variant will be used for, the bonding substance 1102 can be conductive or non-conductive, i.e. an electrically conductive substance such as solder, metal or alloy that can be applied through, for example, electroless or electroplating techniques or deposited by evaporative deposition or sputtering, or a non-conductive bonding agent like, for example, an appropriate type of glue or epoxy or oxide like silicon dioxide.

FIG. 12 is a top view of the upper surface 116 of the specified area 124 of FIG. 1 following the optional introduction of the bonding substance 1102 into the remaining void 1100 of via trench 702 shown in side view in FIG. 11.

FIG. 13 shows a simplified cutaway view of the portion 100 of FIG. 1 as a result of the optional processing as follows.

Alternatively or additionally, if the metallization has not completely filled the void, once the metallization is finished, the remaining void 1100, if any, can optionally be partially or wholly filled with, for example, a simple finishing substance 1302. Depending upon the particular implementation this variant will be used for, the finishing substance 1302 can be, for example, an insulator such as the insulating material 500 that was initially used to fill the trench 302 a conductor such as a conductive epoxy, a conductive solid, or a reflow able material, otherwise a conformal coating can be used. In addition, the finishing substance 1302, if used, need not be introduced solely into the void 1100. As shown in FIG. 13, if it is an electrical insulating material and a bonding substance 1102 has been used, the finishing substance 1302 can be inserted after and on top of any such bonding substance 1102 and can extend outside the void 1100 so as to cover and protect some part of the outer surface of the wafer and/or a part 1304 of the trace 902 that extends to the contact 904, or, even if there is no void, to planarize the wafer. For example, the finishing substance 1302 could be an oxide that can be flattened and thereby planarize the wafer so that the full surface can be used for bonding to another element like a wafer or individual chip.

FIG. 14 is a top view of an insulator upper surface 116 of the specified area 124 of FIG. 1 following the optional addition of the finishing substance 1302 into the remaining void 1100 on top of the bonding substance 1102 as shown in side view in FIG. 13 and in sufficient quantity to provide covering and protection for at least a part 1304 of the trace 902.

Returning to the basic process, FIG. 15 shows a simplified cutaway view of the portion 100 of FIG. 1 as a result of continued processing as follows.

Once the metallization aspect shown in FIG. 9 and FIG. 10 is complete (whether or not one or both of the optional aspects shown in FIG. 11 through FIG. 14 are used) the back (i.e. non-device carrying) side 118 of the substrate 112 is thinned using, for example, a chemical process such as etching, a mechanical process such as polishing, a chemical mechanical process (CMP) or some combination thereof, at least until the bottom metallization 1502 is exposed, thereby creating an electrical contact 1504 on the back 118 of the substrate 112 that is electrically connected to the device contact 904 that is electrically isolated from the doped semiconductor material 122 (in this case the bottom mirror 110 of the laser 104) without the need for performing any specialized backside processing.

Alternatively, the thinning can be performed until the bottom metallization 1502 is removed or the void 1100 volume is exposed (whether filed or not). FIG. 16 shows a simplified cutaway view of the portion of FIG. 15 following thinning of the substrate to remove the bottom metallization. Advantageously, if the approach of at least FIG. 11 and FIG. 12 was used, the void 1100 was filled with a bonding substance 1102. Thus, as shown in FIG. 16, thinning the back side 118 of the substrate 112 until the bottom metallization 1502 of FIG. 15 is removed exposes the bonding substance 1102 while leaving an “annulet” of metal contact 1602 that can still serve as part of the back side electrical contact. Thus, if the bonding substance 1102 is electrically conductive, for example solder, the annulet 1602 and the bonding substance 1102 together act as the contact, whereas if the bonding substance 1102 is not electrically conductive, it can still be used to bond the chip to another element while the annulet 1602 acts as the contact and provides an electrically conductive path from the back side 118 to the device contact 904.

Alternatively, the arrangements of FIG. 15 or FIG. 16 could be thinned so that the metallization or metal contact protrudes beyond the bottom of the wafer for use as a contact in the post and penetration approach alone or with a tack and fuse approach as described herein.

It should now be appreciated that above basic process, as well as the more complex alternative processes that follow and build upon the basic process, provide a further advantage over the prior art in that making of the vias before fabrication of the devices (e.g. transistors, diodes, lasers, photodetectors, etc.) on the wafer is not required. Moreover, the process does not require that the vias only occur in on the periphery of the chip in areas where conventional wirebond pads would occur. Instead, the instant process is more localized and can be performed at sufficiently low temperatures such that circuitry can be formed on or embedded in the semiconductor before via formation and the vias can be placed in areas other than the periphery of the chip. This makes it possible to use the process with chips made by others, without the need to be involved in the design process of those chips, and as will be described in greater detail below, to make connection paths between devices on different chips much shorter than could be done through the use of wirebond pads. Still further, because the process facilitates making paths through the wafer, as described in greater detail below, the process is highly useful for chip stacking or for creating mix and match chip “units”.

One problem that can arise in connection with the filling of a trench with an electrically insulating material, particularly when the trench is narrow in width and relatively deep, for example 100 microns or more in depth, is the possibility of there being pinholes, air bubbles or other imperfections in the electrically insulating material. These imperfections, if extant, could result in an undesirable conductive path between doped semiconductor material of a device the trench passes through and a conductor within it.

Advantageously, if this is a potential problem or concern, the alternative variant shown in FIG. 17 through FIG. 23 can render the problem or concern moot.

FIG. 17 shows a simplified cutaway view of the portion 100 of FIG. 5 as a result of processing according to this alternative variant as follows.

As with FIG. 7, a via trench 1700 is created however, unlike FIG. 7, the entire island 306 of semiconductor material 122 within the annulus 704 of insulating material 500 is not removed. Rather, the via trench 1700 is smaller than that of FIG. 7 so that a perimeter annulus volume 1702 of semiconductor material 122 remains. Since the perimeter volume 1702 of semiconductor material 122 is bounded by the insulating material 500 and the substrate 112, it is electrically isolated from the semiconductor material 122 of the device 104. In addition, since the overall semiconductor material 122 is more perfectly and uniformly formed, any imperfection in the insulating material 500 within the trench 302 will be isolated from metallization in the via 1700 by the perimeter volume 1702 of semiconductor material 122. Other than the above, the approach is the same as described in connection with FIG. 7. Thus, the via trench 1700 is similarly made to a depth 1704 that extends to within the substrate 112 (but preferably not fully through it), for example, by a further etching process or through another suitable process, for example, laser drilling. Once the via trench 1700 has been created, the sidewall(s) 1706 of the via trench 1700, as well as the bottom 1708 of the via trench 1700, will all be electrically non-conducting as described above, but the sidewall(s) 1706 will be the isolated semiconductor material 1702 surrounded by the annulus insulating material 704.

FIG. 18 is a top view of a section taken at A-A below the specified area 124 of FIG. 1 following the creation of the via trench 1700 within the annulus of semiconductor material 1702 that is bounded by the electrically insulating material 704 as shown in side view in FIG. 17.

FIG. 19 shows a simplified cutaway view of the portion 100 of FIG. 5 as a result of further metallization processing of this alternative variant of FIG. 17 in the manner described in connection with FIG. 9.

FIG. 20 shows a simplified cutaway view of the portion 100 of FIG. 5 as a result of further optional processing of this alternative variant of FIG. 17 in the manner described in connection with FIG. 11.

FIG. 21 shows a simplified cutaway view of the portion 100 of FIG. 5 as a result of further optional processing of this alternative variant of FIG. 17 in the manner described in connection with FIG. 13.

FIG. 22 shows a simplified cutaway view of the portion 100 of FIG. 5 as a result of thinning the substrate to expose the bottom metallization 1502 in the manner described in connection with FIG. 15 for the alternative variant of FIG. 17.

FIG. 23 shows a simplified cutaway view of the portion 100 of FIG. 5 as a result of thinning the substrate to remove the bottom metallization 1502 and expose the bonding substance 1102 in the manner described in connection with FIG. 16 for the alternative variant of FIG. 17.

Based upon the above, further alternative variants can be created having dual isolated (i.e. coaxial or coax) conductors. This is advantageous because dual conductors allow for greater contact density and can reduce cross-talk. In addition, with the dual conductor variants, as will be seen, the outer conductors are separated electrically from the inner conductor allowing them to operate at different voltages; for one conductor to operate as a electromagnetic interference (EMI) shield to protect against signal noise, or to allow the signals to propagate differentially through the structure so that lower noise data transfer can occur. Moreover, as with the single conductor approach, only one lithography defined precision etch is performed, the annular trench. As will be seen below, removal of the central material is controlled by the boundary metal and thus is not subject to process variations inherent in photolithographically defined steps or etching. Thus, even this approach is more reproducible and process robust.

Two example coax variants are illustrated in FIGS. 24 through 29B as follows. These variants are suitable for cases where the outermost conductor can be in direct contact with the semiconductor material without adverse effect. Example alternative coax variants follow thereafter in FIGS. 30A and 30B. The alternative dual conductor variants of FIGS. 30A and 30B are analogous to and improve upon the alternative variant shown in FIG. 17 through FIG. 23 and thus likewise suitable to render the same problems or concerns moot.

Initially, the basic dual-conductor creation process follows the approach described in connection with FIGS. 1 through 3. Since this variant builds upon those described previously, for simplicity, only those additional or different aspects relevant to this variant are discussed, the remainder being discernable from the preceding discussion. Thereafter, the processing according to this dual conductor alternative variant is as follows. First, as shown in FIG. 24, at least the sidewalls 304 of FIG. 3 are metalized 2402 as described above. Note that the lowest surface 2400 of the trench 302 may, or may not, be metalized but, as will be evident from the following, this will not affect the ultimate result. FIG. 24 shows a simplified cutaway view of the portion 100 of FIG. 3 immediately following metallization according to this variant.

Following metallization, at least the trench 302 is filled with the electrically insulating material 500. The result of this step is shown in FIG. 25.

Again, as shown in FIG. 26, a via trench 2600 is created by removing the entire island 2406 of semiconductor material 122 bounded by the inner perimeter of the annulus 2602 of metallization 2402.

Alternatively, as shown in FIG. 27, an approach similar to that of FIG. 17 can be employed at this point (i.e. instead of removing the entire island 306 of semiconductor material 122 within the annulus 704 of insulating material 500, only an inner portion is removed 2702 so that a perimeter annulus volume 2704 of semiconductor material 122 remains).

Otherwise, and thereafter, the approach is essentially the same as described previously. The via trench 2600, 2702 is made to a depth that extends to within the substrate 112 (but preferably not fully through it), for example, by a further etching process or through another suitable process, for example, laser drilling or ablation.

The via trench 2600, 2702 is then filled with a conductor 2802 and the substrate is thinned as described above. In the case of the first example dual-conductor variant (FIG. 28A), until the bottom metalizing is removed and the inner conductor 2802 is exposed on the substrate 112 side as shown in FIG. 28B. In the case of the second example dual-conductor variant (FIG. 29A), thinning is performed until the lowermost portion of the metallization is exposed along with the inner conductor as shown in FIG. 29B. Note that in the variant of FIG. 28B, one conductor is made up of the outer ring of metalizing 2804 and the other is made up of the inner ring of metalizing 2806 plus the inner conductor 2802 because the two abut and hence, are shorted together, whereas in the variant of FIG. 29B, one conductor is made up of the metalizing 2402 and the other is made up of the inner conductor 2802.

Thus, in dual-conductor variants such as shown in FIG. 28B, it is highly desirable to make sure that the depth of the annulus 704 and the depth of the via trench 2700 are both beyond the point to which the substrate will ultimately be thinned. In other words, if the overall thickness of the wafer is 500 microns and the wafer substrate will be thinned by 200 microns, the depth of the via trench 2700 must be at least 300 microns plus the likely metallization thickness and, consequently, the original depth of the annulus 704 would have likely needed to be even more than that of the via trench 2700. The reason for this requirement is that electrical isolation between the two conductors is necessary. The above also is the reason why, in some implementations, a failure to coat the lowest part of the trench 302 will have little to no impact, because it is removed during the thinning process anyway.

Based upon the above, it should be recognized that a further alternative coax variant, similar to that of FIG. 28B or 29B, can be created merely by making the sidewalls of the trench non-conductive prior to metalizing. This can be accomplished by, for example, applying a thin coating of dielectric to the sidewalls through dielectric sputtering, plasma deposition, or by pre-creating the initial annular trenches (i.e. before electronic device fabrication) and using a thermal or steam oxidation technique. This technique involves exposing the sidewalls to a reactive gas so, in the case of a silicon wafer, it is oxidized (the conceptual equivalent of causing iron to rust) to form a thin coating of silicon dioxide on the sidewall surfaces. In general overview, the oxidation of the silicon can be performed in a steam environment in accordance with the Deal-Grove model. This approach causes the oxidation to occur in a highly controlled and accurately reproducible manner. Analogous processes can be used to create a coating of silicon oxy-nitride or silicon nitride. Advantageously, with this variant, because the resulting oxide is not deposited—it is thermally grown—it forms evenly and thereby does not introduce the problems inherent with applying a dielectric in liquid, viscous, paste or other form. Moreover, it creates a highly uniform, extremely controllable dielectric material coating, to depths of a millimeter or more, across 12 inch silicon wafers to extremely precise tolerances. Still further, this process has the effect of smoothing the sidewalls, thereby aiding in more uniform metallization.

Of course, it will be understood that this further alternative variant may be unsuitable for some applications, due to the dielectric constant of silicon dioxide, silicon oxy-nitride or silicon nitride, or impossible to implement for others due to other factors not pertinent to an understanding of the subject matter described herein. Otherwise, the approach is the same as described in connection with any of the variants described above in connection with FIGS. 24 through 29B.

For completeness, examples illustrating adding the optional additional thermally created dielectric or insulator 3002 aspect to the approaches of FIGS. 28 and 29 are respectively illustrated in FIGS. 30A and 30B. It should also be appreciated that, in some variants of FIG. 30B, namely those having only partial removal of the inner island so as to leave an annulet of semiconductor material about the via trench, the thermally created dielectric approach can be used to form a dielectric coating on the remaining annulet—provided that aspect is also performed either prior to device creation, following taking suitable measures to ensure the process will not damage any devices that have already been formed in or on the chip, or on a chip where any devices that are in or on the chip are impervious to the process.

Alternatively, the partial removal can be an inverse partial removal, i.e. the inner island is removed from the via trench inward, leaving a smaller island within the via trench. With this variant, the smaller island can serve as a post upon which a contact can be built up and connected to the metallization or conductor. Similarly, the partial removal can be a partial removal from the depth perspective, leaving a well or recess that can be used as the female part of a male/female connector or, if made conductive, can serve as an electrical contact.

Advantageously, it should now be apparent from the above that, as shown in FIG. 31, a three-conductor (i.e. triaxial or triax) variant can also be constructed merely by taking the approach resulting in FIG. 28B but thinning to the extent shown in FIG. 28A (i.e. until the metallization material at the bottom of the trench is completely removed). This three conductor variant is advantageous because it allows the outer metallization to act as a shield between the inner metallization and/or conductor and the device bearing semiconductor material nearby, the metallization between the outer metallization and the inner conductor to act as either a shield between the two, or as a third conductor. Thus, the same three-conductor variant provides several alternative advantages in its own right. Of course, it is to be understood that, in view of the relationship between the single-conductor, two-conductor and three-conductor variants, all options described for use with any one (i.e. coatings (thermally created or applied), void-filling, post and penetration contacts (described below), etc.) are generally interchangeably applicable to all.

As briefly noted above, it is not necessary that the remaining void existing after removal of the central island of material be filled with anything at all. Moreover, in some implementations described herein there are specific advantages to not doing so.

FIG. 32 shows a simplified cutaway view of a portion 100 of a chip implementation, (similar to the implementation of FIG. 9 through FIG. 16 except the void 3210 remaining after metallization has not been filled at all) positioned above an electronic chip 3200 to which the chip 102 will be hybridized so that the contact pad 3202 on the electronic chip 3200 that is to be electrically connected to the top contact 904 of the laser 104 is beneath the void 3210. A solder bump or other softenable, deformable, electrically conductive material 3204 rests on the contact pad 3202 and will be used to physically and electrically bond this portion of the two chips 102, 3200 together either through capillary action or deformation upon insertion with pressure.

FIG. 33 shows a simplified cutaway view of a portion of an alternative chip implementation, similar to that of FIG. 23 except, as with FIG. 32, the void 3310 remaining after metallization has not been filled, positioned above an electronic chip 3300 to which the chip 102 will be hybridized so that the contact pad 3302 on the electronic chip 3300 that is to be electrically connected to the top contact 904 of the laser 104 is beneath the void 3310. A solder bump 2404 rests on the contact pad 3302 and will be used to physically and electrically bond this portion of two chips 3302, 3300 together.

By not filling the void 3210, 3310 in the implementation of FIG. 32 or FIG. 33, capillary action can be used to draw the solder 3204 into the void 3210, 3310 or pressure can be used to cause the deformable material 3204 to deform and enter into the voids, and thereby a) insure a good electrical connection and b) aid in alignment of the chips to each other.

FIG. 34 and FIG. 35 each show the respective cross sections of FIG. 32 and FIG. 33 following hybridization of the chips to each other. As can be seen, the solder 3202 has been drawn up into the respective voids 3210, 3310 with the contact 3206, 3306 of the chip being relatively centered over the contact 3202, 3302 of the respective electronic chip 3200, 3300 to which it is hybridized.

As shown in FIG. 36 for the implementation of FIG. 34 (although the same is equally true for the implementation of FIG. 35 but not shown), coating with an insulator or conformal coating 3600 can optionally be performed.

As briefly noted above, irrespective of the variant used, the annulus trench described above (as well as the perimeter of semiconductor material if that variant is used) can be any closed shape. However, as an extension of the above, it should also be understood that the via trench need not be the same shape as the annulus trench nor does the width of the annulus trench have to be uniform, although in most implementations both will be the same shape, for ease of implementation reasons as well as capacitance or resistance or both. FIG. 37a through FIG. 37f show a few representative examples of cross sections of annulus trenches to illustrate the point. In FIG. 37a, the annulus trench 3702 is illustrated as being triangular. As a result, the width 3704 of the trench 3702 is larger at the points 3706 of the triangle than at the sides 3708. In FIG. 37b, the annulus trench 3710 is illustrated as being rectangular. As a result, the width of the trench 3710 is larger at the corners 3712 than at the sides 3714 and the long sides 3716 are spaced farther apart than the short sides 3718. In FIG. 37c, the annulus trench 3720 is illustrated as being bounded by two different ovals. As a result, the overall width of the annulus trench 3720 varies with position. In FIG. 37d, the annulus trench 3722 is illustrated as being square. As a result, the width of the trench 3722 is larger at the corners than at the sides but the sides are uniformly spaced apart. In FIG. 37e, the annulus trench 3724 is illustrated as square at the outer perimeter 3726, but circular at the inner perimeter 3728. In FIG. 37f, the annulus trench 3730 is illustrated as circular at the outer perimeter 3732, but square at the inner perimeter 3734. In FIG. 37g, the annulus trench 3736 is a convexo-concave (or kidney-like shape) shape where the outer perimeter 3738 and the inner perimeter 3740 are scaled versions of each other and the width of the trench is constant. In FIG. 37h, the annulus trench 3742 has an outer perimeter 3744 similar in shape to that of FIG. 37g and an inner perimeter 3746 of hexagonal shape.

An extension of the above applies equally to the variants that have an annulus of semiconductor material in addition to the annulus of insulator, i.e. the shape of each peripheral surface can be the same as the others or one or more can be different from one or more of the others as desired or as needed for the particular application.

In addition to the advantages obtainable, per se, from use of the above to ultimately create connections between two chips, the above approaches provide significant advantages in the area of chip, die or wafer stacking, particularly where the chip, die or wafer is pre-processed, e.g. it is fully formed from a function standpoint in that it already has whatever functional devices in terms of the transistors, capacitors, diodes, switches, resistors, capacitors, etc. it will contain created on it.

Creating vias using the annular via process provides a way to stack wafers in a manner which allows electrical conductivity and also requires little or no post-processing of the after the wafers are fused. This is highly beneficial, both on a cost and yield basis, particularly at the wafer level where two wafers are to be hybridized together or a wafer is to be populated with multiple individual chips. When putting wafers together, one of the key realizations is that the hybridized two-wafer piece (i.e. after putting two wafers together) has a much higher value than a single wafer piece (i.e. the single wafer immediately prior to hybridization). Likewise if three wafer pieces are stacked together, the value is even higher. Any post-processing that has to be done to a series of stacked dies after they are integrated adds a lot of risk because damage will result in scrapping a very high-value added piece.

Thus, the above processes provide a much better approach because all of the via processing and thinning occurs before the devices are stacked. As a result, fully stack-ready pieces are created that can just be layered one on top of another for joining (i.e. hybridization) with no additional wafer processing, via formation having been done post creation of the on-chip devices and prior to hybridization. As chips are stacked with the above approaches, while the value of the combination goes up and up, the number of steps to attach another layer is typically just one, namely—attach the next die (unless thinning is necessary and was not performed prior to the hybridization). This minimizes the risk of yield loss to expensive parts due to post processing inherent in stacking prior art where chips are stacked and thereafter, electrical contacts are created.

Thus, in contrast to the prior art, creating the vias before stacking allows for:

1) reduced or no post-processing on the stacked piece (resulting in less labor and higher yield); and

2) greater alignment tolerance (each chip only needs to be aligned well relative to the one immediately below (as opposed to stacking prior art which requires all pieces to be aligned in common relative to the bottom piece)).

FIG. 38 illustrates in simplified form, a generic overview form a process for preparing a wafer for stacking FIG. 38A shows in simplified form a portion of the initial, fully formed wafer and, specifically a device 3802 and its underlying substrate 3804. The generic process is as follows. First, a material 3806 is deposited on the device side of the wafer (FIG. 38B). Then, the material 3806 and underlying locations for contacts are etched to create trenches 3830 (FIG. 38C). The walls 3810 of the trenches 3808 are insulated 3812 to prevent potential shorting of doped semiconductor material to the contact to be created (FIG. 38D).

Alternatively, the material 3806 can be created “automatically” during the deposition of the insulating layer 3812. For example, we have put TEOS (oxide) on the wafers by eliminating the first deposition of the material 3806, etching the trenches 3808, then depositing TEOS. Because of the way this material deposits, it placed 2.5 microns of material on top of the wafer and 1.25 microns on the walls in the trenches. This provides an alternative approach to getting a thick top layer while still covering the walls of the trenches. In other words, with this alternative, putting the material 3806 on as a separate step could be eliminated or be used in conjunction with the remaining steps depending upon the topology of the wafer.

Metal 3814 is then introduced into the trenches to provide a seed layer for plating of a conductor (FIG. 38E). Then the remaining via volume is filled with the metal 3816 that will be the conductor (FIG. 38F). Next, the excess metal (and optionally some of the material 3806 and/or insulating layer 3812) is removed, for example by a chemical or mechanical process or some combination thereof (FIG. 38G). Then, the wafer is etched to create openings 3820, 3822 that provide access to the original, existing contact locations 3824, 3826 (FIG. 38H). Next, metal 3828, 3830 is applied to interconnect the existing contact locations 3824, 3826 with the new processing-formed contacts 3832, 3834 (FIG. 38I). Next, the back side 3836 of the wafer is thinned to expose the other end of the processing-formed contacts 3832, 3834 and optionally to remove the insulator 3812 at the bottom of the trenches 3808 (FIG. 38J). Then, the back side 3836 of the wafer is etched to create upraised posts 3838, 3840 and, if the insulator 3812 at the bottom of the trenches 3808 was not removed in the prior step, to remove the insulator 3812 (FIG. 38K). Alternatively, in some implementations, the insulator 3812 could be partially removed or, in some cases not removed at all if electrical conductivity is not required, for example, if it is to be used to simply align or to create a non-electrical post-type connection. Finally, if the exposed fill material that became the post is of a type that can oxidize or otherwise react in a manner that is adverse to later forming a connection, an optional barrier layer 3842 can be applied on the upraised posts 3838, 3840 to prevent oxidation or such other adverse reaction.

In still other alternative variants, the steps of FIG. 38J, FIG. 38K and FIG. 38L can be performed after applying a malleable material (for use as described below) on top of the metal 3828, 3830 and protecting it. This variant reduces the number of steps that have to be performed after the wafer is thinned.

At this point, a generic through-chip connection has been created that can facilitate stacking on a chip, die or wafer basis and thereby form one or more multi-wafer units.

FIGS. 39 through 41 generically illustrate portions of example chips processed to create through-chip connections using different variants of the above-described processes that have, thereafter, been stacked together to form such a unit. Specifically, FIG. 39 shows corresponding portions 3900 of a series of stacked chips interconnected with each other using the basic approach variant. FIG. 40 shows corresponding portions 4000 of a series of stacked dual-conductor variant chips. FIG. 41 shows corresponding portions 4100 of a series of stacked three-conductor variant chips. It should now be appreciated from the above that by employing one of the processes described herein, stacks and units can be formed from wafer components that need not be organized in a coplanar manner or even a fully overlapping manner, but can nevertheless extend in the vertical direction.

Note that, in each of the three stacks of FIGS. 39 through 41, optional contact pads 3902, 4002, 4102, 4104 have been added as standoffs to ensure proper clearance and good electrical contact between wafers.

Depending upon the particular application in which the above will be used, the contacts can be formed in a number of ways. For example, the vias can be micro bumped with, for example a C-4 solder type process of the prior art, so that two points to be electrically connected are placed into contact and the solder is changed to a liquidus state and then hardened so that the two pieces will be physically and electrically joined. In other variants, a pair of contacts can be used where one contact of the pair is rigid and the other is malleable relative to the first and a process as described herein is used to join them. In yet other variants, both contacts in the pair can have malleable material on them and an appropriate process as described herein or otherwise is used to join them. Alternatively, a post and socket type approach of the prior art can be used. With this approach, the two contacts to be joined are made in complementary shapes where either the post is slightly oversized relative to the socket or the socket is slightly undersized relative to the size of the post such that bringing the two together results in an interference fit between the two.

In certain cases, it is desirable to use thicker wafers 4202 (FIG. 42A) to ensure strength in handling. In situations where a wafer is particularly thick and the diameter of a desired via is less than about 1/20th to 1/30th of the desired thickness of the wafer an alternative process can be used for some variants to accommodate the thicker wafer. The process of forming such “back to front” vias is illustrated in simplified form in FIGS. 42B through 42E. First, a via 4204 is etched into the back side of the device-bearing wafer 4202 (FIG. 42B). Then, the via 4204 can be made conductive using one of the processes described herein (i.e. single conductor, coax, triax, etc.) or through some other process like inserting a pre-formed post 4206 (FIG. 42C). The approach can result in the back side having either a malleable material or a rigid post material. Then, a corresponding via 4208 is etched over the conductor 4206 from above (i.e. the front or device side) down to where the bottom of the back side conductor 4206 ends (FIG. 42D). Next, optionally, the front side devices are protected and, if desired, contacts to devices or rerouting is performed (not shown) using, for example, an approach described herein, and the via is made conductive in essentially the same manner as used for the back side (FIG. 42E). Advantageously, with some variants, the material at the bottom of the back side conductor can serve as an etch stop and/or a seed layer for plating the conductor from the front side. This can reduce the number of processing steps relative to the approach used to form the conductor on the back side. Moreover, with other variants, if it is desired that there be no physical connection between the conductor from the back via and the conductor from the front via, a suitable amount of wafer can be left between the two with the connection being made through capacitive coupling.

The approach works with both traditional via processes where a single via is performed and insulator and metals are deposited in one hole or in our previously described process with the annular via approach to create highly controlled impedance vias.

In addition, the back to front approach can be used where one side has a non-completely filled via so that the unfilled part of the via can serve as a “slot” 4210 (FIG. 42F) that will receive a “post” (i.e. a pressure or interference fit connection and thereby provide for alignment and/or physical connectivity as well as electrical connectivity. This type of pressure or interference fit aspect is illustrated in FIG. 42F.

In another alternative variant, the back-to-front method of via creation described above can be used to create a connection only part-way through the chip in such a way so that capacitive coupling can be used to send data between the chips. Because capacitive coupling works when the contacts are closer, and because the density of connections is limited by crosstalk, variants of approaches described herein are ideal for creating chips using this type of communication. These approaches readily allow for minimization of crosstalk by close connections, because it is possible for the distance between the contacts to be minimized and through use of coax or triax posts so that shielding can be provided. Moreover, capacitive contacts have the advantage that no actual electrical contact between the parts is necessary. With this approach, shown in FIGS. 43A through 43D, vias 4304 are etched from the back of the chip 4302 (FIG. 43B) in such a way that they are close enough to the contacts on the top of the chip 4302 so as to be physically removed from the contact but, when filled, are sufficiently close to allow for good capacitive coupling of an applied signal between the fill and the contact. The vias 4304 are then filled with metallic studs, single conductor, coax or triax conductors 4306 to allow good capacitive coupling (FIG. 43C). In this way the wafers can be kept at an overall thickness which allows sufficient strength for handling of the wafers while the connections have the appropriate distance. This approach provides the further advantage that it allows stacking to occur by stacking the back of one wafer to the front of another wafer. In this way multi-stacking of chips 4308, 4310 can occur as shown in FIG. 43D. This is in sharp contrast with an approach that would require the chips to be face-to-face rather than front-to-back because such an approach does not readily allow for multi-stacking of chips to occur (i.e. stacking of three or more chips) since a third chip would have to be on the back of one of the other two chips and then communicate through an entire wafer, requiring sparse contact densities to avoid the prospect of crosstalk. Of course, with the approaches described herein, coax or triax-like vias can be used to enhance shielding of signals to prevent crosstalk.

In addition, capacitive coupling can be used with a pressure fit connection if, for example a true back to front connection is not created in that the two vias do not linkup (i.e. material is left between the via created from the front side and the back side post). In such a case, the front side via will be independently created according to one of the variants described herein, as will the back side via.

Still further, capacitive coupling can occur between one or more contacts on a chip surface (whether created through a via approach or other approach). This may be desirable if, for example, with a stacking approach, chip heights do not allow for two complementary contacts to easily physically touch although they are close together because, for example there is a chip or metallization or other topology maintains a separation between the two, or one or both are covered by an insulator, like TEOS, a photoresist or some other oxide.

From the foregoing, the versatility of our approaches should be more apparent. Advantageously, even further variants can be created that illustrate the broad and versatile range of possibilities available through use of our approaches. One such variant, shown in FIG. 44A through 44I, is a “pre-connect” variant which differs from the above and other approaches because the wafer to be processed 4401 gets attached to an underlying pre-formed wafer 4402 (referred to herein as a “base” wafer) before any processing as described herein begins (i.e. before the annular trench is formed). In this variant, any of the basic connection forming processes can be used. This variant process proceeds as follows.

First, the initial wafer 4401 is thinned to the extent necessary to ensure that the via can go completely through the substrate (FIG. 44A). This step is optional, and need not be performed if the particular etching process that will be used can go entirely through the entire chip without difficulty. Then, the initial wafer 4401 is aligned (FIG. 44B) and attached to the base wafer 4402 (FIG. 44C) using a bonding material, wafer fusion or, if the wafers are very flat, through covalent bonding. Next, annular vias 4404 are created in the initial wafer 4401, over the pads of the base wafer 4402, extending down to the base wafer 4402 such that the via surrounds the pad of interest on the base wafer (FIG. 44D). The annular via 4401 is then filled with an insulator 4406 so that subsequent conductor deposition is isolated (FIG. 44E). Then, all or part of the central post is etched away down to the pad of interest on the base wafer 4402 in order to create a void 4408 above the base wafer\'s pad (FIG. 44F). Finally, the void 4408 is metalized (FIG. 44G) and optionally either fully filled with a conductor 4410 (FIG. 44H) using one of the approaches described herein or if the metallization does not fully fill the center of the void 4408, it can be filled with an insulator 4412 (FIG. 44I). As a result, the metal filling forms an electrical connection to the base wafer 4402 pad and effectively extends the base wafer pad up through the initial wafer 4401 and physically bonds the two chips together. Advantageously, by using this approach the central post of the semiconductor material protects the base wafer\'s pad so that no insulator interacts with the base wafer pad. This is markedly different that what would happen if conventional approaches were used to try the same thing because those conventional approaches would leave the base wafer pad exposed and thus would allow contamination by the applied insulator.

In some cases however, the pressure fit connection approaches will not be suitable because of a lack of control-ability. For those instances, an optional alternative approach we have devised called a “post and penetration” approach can be used. Ideally, the post and penetration approach can, and typically will be, used along with a “tack and fuse” process owing to the advantages each provides alone and the further advantages provided by their use in combination.

The approach involves the use of two contacts in combination: a rigid “post” contact and a relatively malleable (with respect to the post material) pad contact, in some cases, either or both having an underlying rigid supporting structure or standoff In simple overview, one of the two contacts is a rigid material, such as nickel (Ni), copper (Cu) or palladium (Pd) or other suitably rigid alloy such as described herein. This contact serves as the “post.” The other of the two contacts is a material that is sufficiently softer than the post that when the two contacts are brought together under pressure (whether from an externally applied force or a force caused, for example, by flexation of the wafer) the post will penetrate the malleable material (the “post and penetration” part) and heated to above a pre-specified temperature (the tack phase of the tack and fuse process) the two will become “tacked” together upon cooling to below that temperature without either of them reaching a liquidus state.

Note that, as used herein, the term liquidus is intended to mean a state in which the metal or alloy being discussed is in a fully (or substantially fully) liquid form. When a metal is in a non-liquidus or semi-liquidus state, as used herein, the metal is sufficiently soft to allow for attachment as described herein, but is insufficiently liquid to allow it to run or flow like the same metal or alloy would in a pure liquid or liquidus state. Most variants of our processes operate with the metal or alloy in a non-liquidus and non-solidus state. Stated another way, on a phase diagram for the metal or alloy, our process variants operate between the solidus (fully solid) and liquidus (fully liquid) temperatures, with most operating near the equilibrium point between the two. This difference can be further understood with reference, for example, to the joining a chip to another element as illustrated in FIG. 33 through FIG. 36. In those figures, if the material 2404 is a solder (metal or alloy) in the liquidus state it will cause the chip to “float” on the melted solder and the vias 3210, 3310 would self-center over the solder ball as capillary action drew the solder up into the via 3210, 3310. In a non-liquidus or semi-liquidus state, such as used for most variants of the tack and fuse process described herein, the state into which the metals or alloys are driven during both the tack phase and fuse phase are such that the metal or alloy would be highly softened (i.e. have some material in a liquid state) but not be sufficiently liquid to cause the chip to float or the vias 3210, 3310 to self center. Thus, some application of force (whether externally applied or resulting from the weight of the chip without external force application), will be necessary to get the metal or alloy into the vias 3210, 3310.

Thereafter, a second heating to above another temperature higher than the “tack” temperature (the fuse phase of the tack and fuse process) will cause materials from each to inter-diffuse (in contrast with a solder which would enter and exit a liquidus state (i.e. melt and re-harden)).

The tack and fuse integration process is separated into two main components: an “attach” or “tack” phase and a “fuse” phase. The tack phase makes a fairly homogeneous electrical connection between the pairs of contacts. The combination of forming a post and penetration connection with the tack process enables any surface oxide on any of the contacts to be more easily broken through. This non-oxide inhibited contact approach allows for a simpler fuse process without the need for application of significant pressure. In the absence of the combination of post and penetration and tack phase, the fuse process would require substantially greater pressure in order to allow the contacts to break through the oxides that would form at the surface of the rigid and malleable materials during the high-temperature portion of the tack process, or in the early stages of the fuse process. By getting beyond that oxide ‘crust’ at the initiation of the tack phase, the fuse phase can occur at substantially lower pressure, in some cases at no added pressure beyond the weight of the chip itself.

At this point, a further terminology convention is introduced. It should be understood that, as set forth herein, the terms “daughter” and “mother” are used, for simplicity, to generally connote whether the particular contact on a wafer being discussed is a rigid or malleable contact, with the term “mother” being associated with a rigid contact and the term “daughter” being associated with a malleable contact. Although shown fairly consistently one way herein, it is important to note that the terms “mother” and “daughter” are arbitrarily applied. Individual contacts on each wafer can be either a rigid or malleable contact as long as the corresponding contact on the other wafer to which it will be joined is of the opposite type. Thus, a given wafer surface can exclusively have one or the other type of contact or, in some variants, a single wafer side can have a mixing of both types. However, mixing of types on a single surface can be problematic for some applications and, in those applications where it is used, mixing of types on a single surface can complicate the processing unless the different types are not intermixed in one area but rather are confined to discrete areas such that large areas will contain only one type of contact allowing areas that will contain the other type to be easily protected when certain processing steps are carried out.

During the attach or tack phase of the process, the “mother” wafer is populated with “daughter” chips. The mother wafer is maintained at a single temperature (i.e. the mother wafer is maintained as an isothermal substrate during this attach process). The isothermal temperature for the mother wafer can be as low as room temperature, although raising the temperature above room temperature speeds up this phase of the process. However, the isothermal temperature is kept below the melting point of the malleable material on the daughter chip as well as the tack or the fuse temperatures. Thus, the tack process can be done by heating each small daughter chip to a higher temperature than the mother wafer so that, when the two chips are brought into contact and a post and penetration connection occurs, the interface for just that chip reaches or slightly exceeds the appropriate “tack” temperature. In general, for the primary materials discussed herein, the tack temperature would be between about 190° C. and about 320° C., with a typical nominal tack temperature of about 270° C. In this manner, the other chips on the mother wafer are not heated beyond the point where their contacts see the elevated temperature, a condition which could change the performance of the contact and cause some contacts to see much longer times at elevated temperatures than others, potentially causing non-uniformity of performance.

The tack or attach process can be performed by, for example, keeping the mother wafer at an isothermal temperature below the malleable temperature, bringing the daughter chip to the mother chip, heated to below the malleable temperature, making contact between the two chips, and quickly ramping the daughter chip temperature to the appropriate tack temperature. Thus, once the daughter chip is attached to the mother wafer, the machinery that aligns the parts (and imparts heat to the daughter chip) releases the daughter chip after applying only enough pressure to allow some contact between the parts, for example less than 2 g/contact pair, and preferably less than 1 g/contact pair.

After release, the cap/adhesion layer (or malleable layer if the malleable material also performs the function of the cap/adhesion layer) on the daughter chip becomes less soft under the decreased temperature which would be dominated by the mother chip at that point. For example, with the baseline materials described herein, the mother chip/wafer substrate can be held at between about 230° C. to 250° C., the daughter chip can be brought to the mother chip at a nominal temperature of about 270° C. and quickly ramped, after contact, to about 310° C. to 330° C. The order of the contacting relative to the quick ramp (i.e. whether it happens before or after contact with the mother wafer) can be changed. Notably, we have found that by bringing the chips into contact first and then ramping up the temperature, oxide formation on the surface of the malleable material can be minimized, thus allowing a more reproducible contact. Advantageously, through use of the malleable material, the amount of pressure per contact pair can be low. We have used applied pressures ranging from about 0.001 g to about 10 g per contact pair although lower bounds are possible, the lowest being the effect of gravity on the mass of the chip itself (i.e. its weight).

In addition, as noted above, for the tack process, daughter wafer temperatures as low as room temperature can be used if sufficient pressure is applied to break through any surface oxides. In this manner, the entire mother wafer can be populated with daughter chips before any tack phase is started. Even using this approach, due to the speed in which the process can occur, the mother wafer does not have time to be heated to any substantial degree. Thus the attachment of a second daughter chip to a mother wafer, even within 100 microns of the first chip in the horizontal or vertical direction does not soften the cap/adhesion layer of the first chip to affect its alignment to any meaningful or substantial degree.

Advantageously, the tack and fuse processes are both typically non-liquidus process. This means that the process is done so that the malleable material becomes softened significantly but does not become completely liquidus during either the tack or fuse processes. This is because if the malleable material were to become liquidus, there would be significant risk that the resultant liquid would run and short out adjacent contacts. By keeping the materials non-liquidus, far greater contact density can be achieved. However, in some variants a semi-liquidus state is allowable (i.e. some, but significantly less than all, of the malleable material may briefly become liquidus). However, those variants generally have the common characteristic of using some other type of containment mechanism to prevent the liquidus malleable material from having an adverse effect by constraining it to a defined area to avoid the possibility of shorting an adjacent contact, for example, by ensuring that the pad onto which the malleable material is applied is surrounded or covered on its periphery by a non-metallic substance into which the malleable material can not easily interdiffuse.

In some variants, in conjunction with the “tack” phase of the tack and fuse process, it may be desirable to cap the malleable material (for example, Au/Sn alloy) with an adhesion layer (for example, Sn) which will melt at lower temperature to help speed-up the tack time to enhance throughput. In addition, in some variants, it may be desirable to keep the mother wafer at an isothermal temperature of the highest possible temperature below the fuse temperature such that no degradation of a bond occurs if the chip sits at that temperature for extended times under non-controlled environmental conditions (i.e. the time it could take to populate a whole wafer in volume). We typically use 230° C. although the temperature could be higher to speed up the process. The impact of the lower temperature is an alteration of the temperature and pressure profile of the penetration phase of the attachment. Moreover, in order to speed up the process, it is desirable to have the serial processes of the tack phase (i.e. place and heat) occur as quickly as possible. A further aspect to note is that, in some variants, the longer the time spent in the tack phase, the less critical the fuse phase is for yield, etc. For example, at one extreme, on an FC150 (for silicon-to-silicon), we had a tack phase lasting for about 1 minute and there was no fuse phase needed. This is summarized in FIG. 45.

At the other extreme, in high volume cases, alignment would typically take about 1 second, the tack phase would take 2 to 4 seconds before the fuse phase. Thus, in those variants the environment for transport from tack machine to fuse phase can be important for getting good contacts.