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Gate driver and liquid crystal display including same

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Title: Gate driver and liquid crystal display including same.
Abstract: Provided are a gate-lines driver circuit and a liquid crystal display (LCD) device including the same. The gate-lines driver may be in danger of being subjected to static electricity and it includes: a wiring unit which receives signals from an external source and a circuit unit which outputs driving signals in response to a plurality of control signals received from the wiring unit. The circuit unit includes a plurality of shift registers, each having shift register wirings, wherein the wiring unit includes first through n-th vertical signal lines arranged sequentially in order of distance from the shift registers, with the first vertical signal line being located farthest from the shift registers. The first vertical signal line is connected to each of the shift registers by a first horizontal connection line, and the first horizontal connection line includes a first contact portion which is formed over and contacting with the first signal line and a second contact portion which is located between the n-th vertical signal line and a boundary of the shift registers and is connected to each of the shift registers by a shift register wiring. The first horizontal connection line is structured to reduce a danger that the shift registers will be burned out by a surge of static electricity current received through the wiring unit. ...


Inventors: Kwi-Hyun KIM, Jang-Soo Kim, Hyeong-Jun Jin, Soo-Chul Kim, Kyoung-Hae Min
USPTO Applicaton #: #20120098800 - Class: 345204 (USPTO) - 04/26/12 - Class 345 


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The Patent Description & Claims data below is from USPTO Patent Application 20120098800, Gate driver and liquid crystal display including same.

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This application claims priority from Korean Patent Application No. 10-2010-0102434 filed on Oct. 20, 2010 in the Korean Intellectual Property Office, the disclosure of which application is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of Disclosure

The present disclosure of invention relates to a gate driver structured such that its elements are better protected against being burned by static electricity and a liquid crystal display (LCD) including the gate driver.

2. Description of Related Technology

Generally, a liquid crystal display (LCD) includes a display panel having a plurality of gate lines and a plurality of data lines, a gate driver transmitting a plurality of gate signals to the gate lines, and a data driver transmitting a plurality of data signals to the data lines.

In a conventional LCD, each of the gate driver and data driver is mounted on a display panel in the form of one or more respective IC chips. However, attempts are being made to monolithically integrate at least one of the gate driver and the data driver on a same substrate having the thin-film transistors (TFTs) of the LCD in order to reduce the total size of the display device and to improve productivity and reliability. That is, a gate driver circuit which generates the gate signals of a TFTs-containing substrate is integrally formed on that substrate using an amorphous silicon TFT technology that directly mounts the gate driver circuit on the same glass substrate where the pixels and their respective TFT switching transistors are formed.

However, when a plurality of amorphous silicon TFTs are disposed on a glass or alike substrate to thus integrally form such a gate driver, static electricity generated in manufacturing facilities may flow to a gate driving circuit through an edge of the substrate and undesirably burn out elements of the gate driving circuit. Since the generation of static electricity in the manufacturing facilities cannot be prevented completely, it is desirable to develop a gate driver structured such that its elements are protected against being burned out by static electricity flowing thereto.

It is to be understood that this background of the technology section is intended to provide useful background for understanding the here disclosed technology and as such, the technology background section may include ideas, concepts or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to corresponding invention dates of subject matter disclosed herein.

SUMMARY

Aspects of the present disclosure provide a gate-lines driver circuit structured such that the danger of its elements being burned out by static electricity is reduced.

Aspects of the present disclosure also provide a liquid crystal display (LCD) including the static electricity tolerant gate-lines driver circuit.

According to a more detailed aspect of the present teachings, there is provided a gate-lines driver circuit including: a wiring unit which receives signals from an external source ( ); and a circuit unit which outputs gate lines driving signals in response to a plurality of control signals received from the wiring unit, where the circuit unit includes a plurality of shift registers, each having internal shift register wirings, and wherein the wiring unit includes first through n-th vertical signal lines that are spaced apart and arranged sequentially to thus define an ordering of respective distance from the shift registers, with the first vertical signal line being located farthest away from the shift registers, where n is a natural number, wherein the first signal line is connected to each of the shift registers by a first horizontal connection line, and the first horizontal connection line includes a first contact portion which is formed on the first signal line and a second contact portion which is located between the n-th signal line and the shift registers and is connected to each of the shift registers by a shift register wiring.

According to another aspect of the present disclosure, there is provided a gate driver including: a wiring unit which receives signals from an external source; and a circuit unit which outputs driving signals in response to a plurality of control signals received from the wiring unit and includes a plurality of shift registers, each having shift register wirings, wherein the wiring unit includes first through n-th signal lines arranged sequentially in order of distance from the shift registers, with the first signal line being located farthest from the shift registers, where n is a natural number, wherein the first signal line is connected to each of the shift registers by a shift register wiring extending to the first signal line, at least one of the second through n-th signal lines is divided into two spaced apart sections that have centered between them a line of the shift register wiring, and the two spaced apart sections are electrically connected (bridged) together by a connection line extending insulatively over the line of the shift register and having plural contact portions.

According to another aspect of the present disclosure, there is provided an LCD including a gate driver formed on a substrate, wherein the gate driver includes: a wiring unit which receives signals from an external source; and a circuit unit which outputs driving signals in response to a plurality of control signals received from the wiring unit and includes a plurality of shift registers, each having shift register wirings, wherein the wiring unit includes first through n-th signal lines arranged sequentially in order of distance from the shift registers, with the first signal line being located farthest from the shift registers, where n is a natural number, wherein the first signal line is connected to each of the shift registers by a first connection line, and the first connection line includes a first contact portion which is formed over and contacts the first signal line and a second contact portion which is located between the n-th signal line and the shift registers and is connected thereat to each of the shift registers by a shift register wiring.

According to another aspect of the present disclosure, there is provided an LCD including a gate driver formed on a substrate, wherein the gate driver includes: a wiring unit which receives signals from an external source; and a circuit unit which outputs driving signals in response to a plurality of control signals received from the wiring unit and includes a plurality of shift registers, each having shift register wirings, wherein the wiring unit includes first through n-th signal lines arranged sequentially in order of distance from the shift registers, with the first signal line being located farthest from the shift registers, where n is a natural number, wherein the first signal line is connected to each of the shift registers by a shift register wiring extending to but not directly connecting to the first signal line, at least one of the second through n-th signal lines is divided into two spaced apart sections between which is disposed a line of the shift register wiring, and the two sections are electrically connected together by a connection line extending insulatively over the line of the shift register wiring and having contact portions.

Other aspects of the present teachings will become apparent from the below detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and features of the present disclosure of invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a plan view of a gate driver and a liquid crystal display (LCD) including the same according to an exemplary embodiment of the present disclosure;

FIG. 2 is an exemplary block diagram illustrating shift registers that constitute the gate driver shown in FIG. 1;

FIG. 3 is an exemplary circuit diagram of a jth shift register shown in FIG. 2;

FIG. 4 is a schematic layout diagram of the gate driver shown in FIG. 1;

FIG. 5 is an exemplary schematic layout diagram of a wiring unit of the gate driver shown in FIG. 1;

FIG. 6 is a cross-sectional view of the wiring unit taken along the line I-I′ of FIG. 5;

FIG. 7 is a layout diagram of a wiring unit of a gate driver according to another exemplary embodiment of the present disclosure; and

FIG. 8 is a cross-sectional view of the wiring unit taken along the line II-II′ of FIG. 7.

DETAILED DESCRIPTION

Advantages and features of the present teachings may be understood more readily by reference to the following detailed description of exemplary embodiments and the accompanying drawings. The present teachings may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the present teachings to those skilled in the corresponding art. In the drawings, sizes and relative sizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to as being “on” another element or layer, the element or layer can be directly on another element or layer or intervening elements or layers may also be present. In contrast, when an element is referred to as being “directly on” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Spatially relative terms, such as “below”, “beneath”, “lower”, “above”, “upper”, and the like, may be used herein for ease of description to describe one element or feature\'s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. Like reference numerals refer to like elements throughout the specification.

Embodiments in accordance with the disclosure are described herein with reference to plan and cross-section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

Also, since a drain (or drain electrode) and a source (or source electrode) may be named differently according to the direction of current, an element called a drain or drain electrode hereinafter may operate as a source or source electrode, and an element called a source or source electrode may operate as a drain or drain electrode. Accordingly, an element called a drain or drain electrode is not limited to the drain or drain electrode. Also, the element called the source or source electrode is not limited to the source or source electrode.

Hereinafter, exemplary embodiments of a gate-lines driver circuit and a liquid crystal display (LCD) including the same will be described in detail with reference to the accompanying drawings.

A gate-lines driver and an LCD that integrally incorporates the same according to a first exemplary embodiment of the present disclosure will now be described with reference to FIGS. 1 through 6. FIG. 1 is a schematic of a gate driver 400 and an LCD 10 including the same according to the first exemplary embodiment. FIG. 2 is an exemplary block diagram illustrating shift registers SR1 through SRn+1 that constitute the gate driver 400 shown in FIG. 1. FIG. 3 is an exemplary circuit diagram of a jth shift register SRj shown in FIG. 2. FIG. 4 is a schematic layout diagram of the gate driver 400 shown in FIG. 1. FIG. 5 is an exemplary schematic layout diagram of a wiring unit LS of the gate driver 400 shown in FIG. 1. FIG. 6 is a cross-sectional view of the wiring unit LS taken along the line I-I′ of FIG. 5.

Referring first to FIG. 1, the display device 10 according to the current exemplary embodiment includes a liquid crystal panel 300, a gate driver 400 integrally incorporated in the panel 300, a timing controller 500, a clock generator 600, and a data driver 700.

The liquid crystal display 300 is divided into a display area DA in which an image is displayed and a non-display or peripheral area PA in which the image is not displayed.

To display the image, the display area DA includes a first substrate (not explicitly shown) on which there are formed a plurality of gate lines G1 through Gn, a plurality of data lines D1 through Dm, a plurality of pixel switching devices (not explicitly shown) and a plurality of pixel electrodes (not explicitly shown) are disposed. Moreover, a second substrate (not shown) is further provided and spaced apart from the first substrate where the second substrate has a plurality of color filters (not shown) and a common electrode (not shown). A liquid crystal layer (not shown) is interposed between the first and second substrates and orientations of its liquid crystal molecules are controlled by electric fields formed between the pixel-electrodes and corresponding portions of the common electrode.

The gate lines G1 through Gn and the data lines D1 through Dm respectively extend on their supporting first substrate in the display area DA thereof and in respective a row and column directions. In addition, switching devices and a plurality of pixels PX connected to the gate lines G1 through Gn and the data lines D1 through Dm are formed in pixel regions PX defined by intersections of the gate lines G1 through Gn and the data lines D1 through Dm.

The non-display area PA is a region in which no image is displayed. One reason why no image is displayed there in the PA area of a given embodiment can be because the first substrate of that embodiment is wider than the second substrate.

The timing controller 500 receives input control signals, such as a horizontal synchronization signal Hsync, a main clock signal Mclk and a data enable signal DE, and outputs an image signal DAT and a first control signal CONT1. The first control signal CONT1 controls the operations of the data driver 700. Examples of the first control signal CONT1 include a horizontal start signal for starting the data driver 700 and a load signal for instructing the output of corresponding analog data voltages. The timing controller 500 sends a vertical synchronization start signal to the clock generator 600 by being synchronized with a vertical synchronization signal Vsync and provides a second control signal CONT2 to the clock generator 600.

The clock generator 600 receives the second control signal CONT2 from timing controller 500 and outputs a clock signal CKV and a clock bar signal CKVB. That is, in response to the second control signal CONT2, the clock generator 600 outputs the clock signal CKV and the clock bar signal CKVB using a gate-on voltage level, Von and a gate-off voltage level Voff. Examples of the second control signal CONT2 include an output enable signal OE and a gate clock signal CPV. The clock signal CKV and the clock bar signal CKVB are pulse signals that swing between the gate-on voltage level Von and the gate-off voltage level Voff. The clock signal CKV may be a reverse phase signal of the clock bar signal CKVB.

The data driver 700 receives the image signal DAT and the first control signal CONT1 from the timing controller 500 and provides corresponding image data voltages to the data lines D1 through Dm, respectively. The data driver 700 may be disposed as monolithically integrated circuits (ICs) whose terminals are connected to the liquid crystal panel 300 in the form of a tape carrier package (TCP). However, the present disclosure of invention is not limited to such discrete coupling of the data driver 700. The data driver 700 may alternatively be disposed in the non-display area PA of the first substrate.

The gate driver 400 may be disposed in the non-display area PA of the first substrate. Although only a one-side version is shown in the drawings, a plurality of the gate drivers 400 may be respectively disposed on two opposed sides of the non-display region PA of the first substrate with the display area DA between them. In the latter case, a gate driver 400a (not shown) disposed on a first side of the non-display area PA of the first substrate may drive, e.g., even gate lines of the gate lines, while a different gate driver 400b (not shown) disposed on the opposite second side of the non-display area PA may drive, e.g., odd gate lines of the gate lines. Alternatively, the gate drivers 400 formed on both sides of the non-display region PA may each drive all of the gate lines G1 through Gn, respectively.

When enabled by a scan start signal STVP, the gate driver 400 generates a plurality of gate signals using the clock signal CKV, the clock bar signal CKVB and a direct current (DC) voltage signal Vss. The gate driver 400 sequentially transmits Von pulses of the gate signals to corresponding ones the gate lines G1 through Gn, one after the next.

Referring to FIG. 2, the gate driver 400 includes a plurality of shift registers SR1 through SRn+1, where n is a natural number greater than one. The shift registers SR1 through SRn+1 receive the clock signal CKV, the clock bar signal CKVB and the DC voltage signal Vss and sequentially provide a plurality of gate signals to the gate lines G1 through Gn. The gate lines G1 through Gn are connected to output terminals of the shift registers SR1 through SRn+1, respectively. The shift registers SR1 through SRn+1 are connected to each other in a cascade manner. The shift registers SR1 through SRn, (this excluding the last shift register SRn+1), are connected to the gate lines G1 through Gn, respectively, and output their corresponding gate signals Gout(1) through Gout(n) to the gate lines G1 through Gn, respectively. That is, the shift registers SR1 through SRn receive the DC voltage signal Vss, the clock signal CKV and the clock bar signal CKVB and a direct or relayed version of the scan start signal STVP and they responsively and sequentially output their respective gate signals Gout(1) through Gout(n), each having a predetermined turn-on level of voltage (Von) for a predetermined period of time, to the gate lines G1 through Gn.

Each of the shift registers SR1 through SRn+1 includes a first clock terminal CK1, a second clock terminal CK2, a set terminal S, a reset terminal R, a source voltage terminal GV (ground voltage), a frame reset terminal FR, a gate signal output terminal OUT1 and a carry output terminal OUT2.

For purposes of explanation, the jth shift register SRj, for example, connected to a jth gate line (where j≠1 and is a natural number ranging from 2 through n−1) will now be described in further detail still with reference to FIG. 2. A carry signal Cout(j−1) of a previous shift register, e.g., the (j−1)th shift register SRj−1, is input to the set terminal S of the jth shift register SRj, the gate signal Gout(j−1) of a subsequent shift register, e.g., the (j+1)th shift register SRj+1, is input to the reset terminal R of the jth shift register SRj, and the clock signal CKV and the clock bar signal CKVB are input to the first clock terminal CK1 and the second clock terminal CK2, respectively, of the jth shift register SRj. (However, in the next shift register SRj+1, the respectiveness between CKV and CK1 versus CKVB and CK2 is reversed. CK1 gets the CKVB signal and CK2 gets the CKV signal.)

In addition, the DC voltage signal Vss is input to the source voltage terminal GV of the jth shift register SRj, and an initialization signal INT or, alternatively, a carry signal Cout(n+1) of a last shift register, e.g., the (n+1)th shift register SRn+1, is input to the frame reset terminal FR of the jth shift register SR1. The gate output terminal OUT1 outputs the gate signal Gout(j), and the carry output terminal OUT2 outputs a carry signal Coutj) for application to the S input of the next stage.

In the case of the first shift register SR1 of the chain however, the scan start signal STVP, instead of a carry signal of a previous shift register of the first shift register SR1, is input to the first shift register SR1. In addition, the scan start signal STVP, instead of a gate signal of a next shift register of the last shift register SRn+1, is input to the last shift register SRn+1. The scan start signal STVP input to the first shift register SR1 is substantially the same as the scan start signal STVP input to the last shift register SRn+1.

The internal circuitry of the jth shift register SRj shown in FIG. 2 will now be described in further detail with reference to FIG. 3. Referring to FIG. 3, The jth shift register SRj includes a buffer unit 410, a charging unit 420, a pull-up unit 430, a carry signal generation unit 470, a pull-down unit 440, a discharging unit 450, and a holding unit 460. Each of the charging unit 420, discharging unit 450, and buffer unit 410 is connected to a so-called node N1 line within the jth shift register SRj. The carry signal Cout(j−1) of the previous shift register SRj−1, the clock signal CKV, and the clock bar signal CKVB are provided to the jth shift register SRj.

The buffer unit 410 includes a transistor T4. A gate electrode and a drain electrode of the transistor T4 are shorted together and connected to the set terminal S of the jth shift register SRj. Since the gate and drain electrode of the transistor T4 are connected to each other, transistor T4 operates substantially like a diode. The buffer unit 410 provides to the N1 node, the high level if present of the carry signal Cout(j−1) of the previous shift register SRj−1, which is received through the set terminal S. In other words, if N1 is low, the buffer unit 410 provides a recharging voltage to the charging unit 420, as well as to the gate of the carry signal generation unit 470, and to the gate of the pull-up unit 430.



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stats Patent Info
Application #
US 20120098800 A1
Publish Date
04/26/2012
Document #
13070394
File Date
03/23/2011
USPTO Class
345204
Other USPTO Classes
345 87
International Class
/
Drawings
7



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