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Semiconductor chip attach configuration having improved thermal characteristics

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Title: Semiconductor chip attach configuration having improved thermal characteristics.
Abstract: An array of metal bodies are attached to a metal carrier by forming Metal bodies form metal inter-diffusions with carrier. The metal bodies are coined to form flattened body ends. A polymeric adhesive precursor is disposed onto the array and a semiconductor chip having a first surface including circuitry and an opposite second surface free of circuitry is attached to the adhesive precursor so that the second chip surface is in contact with the flattened ends of the arrayed metal bodies, which stop at the second surface. ...

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Inventors: Kapil Heramb Sahasrabudhe, Jayprakash Vijay Chipalkatti
USPTO Applicaton #: #20120094441 - Class: 438118 (USPTO) - 04/19/12 - Class 438 
Semiconductor Device Manufacturing: Process > Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor >Including Adhesive Bonding Step

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The Patent Description & Claims data below is from USPTO Patent Application 20120094441, Semiconductor chip attach configuration having improved thermal characteristics.

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This Application is a Continuation of and claims priority to U.S. patent application Ser. No. 12/562,385 filed on Sep. 18, 2009, incorporated herein by reference for all purposes.


Embodiments of the invention are is related in general to the field of semiconductor devices and processes, and more specifically to the structure and fabrication method of thermally improved semiconductor devices having the chips attached to the metallic substrate by metal balls in addition to the metal-filled polymeric adhesive.


Removing the thermal heat generated by active components during device operation belongs to the most fundamental challenges in integrated circuit technology. In order to keep the active components at their optimum (low) operating temperatures and speed, this heat must continuously be dissipated and removed to outside heat sinks. This effort becomes increasingly harder, the higher the energy density gets.

When a semiconductor chip includes the circuitry on one surface, the opposite surface is commonly attached to a carrier such as the metal pad of a leadframe or a substrate. The attachment is usually performed by an adhesive such as an epoxy-based or polyimide-based polymeric resin. The adhesive is applied as a low viscosity precursor, typically by using a syringe to drop a small resin volume onto the carrier. The chip is then pressed onto the spreading compound to form a layer typically between 50 and 80 μm thick. Thereafter, the resin is hardened by polymerization at elevated temperatures (150 to 220° C. for 20 to 30 min), known as the curing process.

The most effective approach to heat removal focuses on transport of the thermal energy from the circuitry through the chip thickness to the attachment surface and then through the adhesive precursor to the chip carrier, which is preferably fully metallic. In order to increase the thermal conductivity of the precursor, silver particles of a length between about 5 to 50 μm are finely distributed in the resin. The most suitable filling coefficient has been found to be between about 80 and 90 volume %, resulting in a compound thermal conductivity λ typically between 3 to 6 W m−1 K−1. Due to the method of application, the silver particles are predominantly oriented horizontally so that the dispersed metal particles are connected only at small points and the interface between chip and compound and the interface between carrier and compound are resin-rich, contributing to the low effective thermal conductivity of the compound.

The steps of applying the low viscosity precursor, pressing the chip onto the compound, and hardening the precursor by polymerization are performed under tight process controls to ensure uniformity of the layer thickness and chemical composition. Unequal uniformity distributions have been found to be sensitive to thermomechanical stresses, fatigue, and the opening of microcracks, which eventually may lead to delamination of the chip from the carrier.


Applicants recognized that the ever shrinking component feature sizes and increasing density of device integration, coupled with an ever increasing device speed and density of power (for example on a power FET, field effect transistor) are resulting in a thermal energy generation, which can no longer be reliably removed by the low thermal conductivity of the polymeric compound layer between chip and carrier. Applicants realized, however, that a filler loading higher than 90 volume %, while increasing the probability of metal to metal contact and thus improving the compound thermal conductivity, would lower the adhesive content and thus reduce the mechanical bonding strength, and would result in higher viscosity leading to dispensing challenges.

Applicants further found that the simple replacement of the adhesive resin layer by a solder layer of tin (λSn67 W m−1 K−1) or of eutectic gold/germanium alloy (12.5 weight % Ge, λAu 317 W m−1 K−1, λGe 60 W m−1 K−1) leads to unacceptable microcracking of the layer and delamination of chip and carrier. In addition, metallic chip attach layers are more expensive than metal-filled epoxy materials and require back side metallization of the chips.

Applicants solved the problem of greatly increasing the thermal conductivity of the chip-to-carrier attachment layer and simultaneously avoiding microcracks and delamination, by first attaching across the carrier area an array of metal bodies, preferably made of copper (λCu 401 W m−1 K−1) or of gold (λAu 317 W m−1 K−1), and then filling the space between these bodies with the silver-filled adhesive compound. When the chip surface opposite to the circuitry-carrying surface is attached to the adhesive, the circuitry-free chip side gets in contact with the metal bodies, which stop at the circuitry-free chip side.

The array of metal bodies may be created by automated wire bonders, which form free air balls from copper wire or gold wire at the tip of a capillary and press the hot balls against the carrier surface for attachment, in the process forming metal interdiffusions between balls and carrier and forming tapered metal bodies resembling truncated cones. After wire break-off, a coining process flattens the body breakage area. The pattern of the array is controlled by the bonder computer and can thus easily be customized for different device types. A preferred pattern includes coined bodies spaced regularly in x- and y-directions in order to dramatically increase the thermal conductivity of the attachment layer generally.

Additional preferred patterns include locally enhanced body concentrations at spots identified of having high stress (such as chip corners) or high temperatures (hot spots of the operating integrated circuit). For the metal body concentrations at high stress spots, applicants have discovered that microcracks in the adhesive, which might originate for instance at the assembly corners, are regularly deflected or outright stopped at the metal bodies. Consequently, concentrations of metal bodies in chip corners make the assembly robust against delamination.

For the metal body concentrations at hot spots of the operating circuit, applicants demonstrated the local cooling effect and thus the prevention of the dreaded second breakdown phenomenon (leading to destructive local melting of silicon) caused by local thermal runaway.


FIG. 1 shows a schematic cross section of a semiconductor device according to the invention, the device having the chip attached to a (metallic) carrier by layer of an adhesive polymeric compound and an array of metal bodies for transferring heat and stopping microcracks.

FIG. 2 illustrates a schematic top view of a semiconductor device carrier with metal bodies attached in an array according to the invention, the array including a regularly spaced pattern in x- and y-directions as well as enhanced concentrations in locations of thermal hot spots and high thermomechanical stresses.

FIG. 3 shows a schematic cross section of a semiconductor device illustrating the flow of thermal energy through the chip attach layer.

FIG. 4 is a schematic top view of a semiconductor device carrier with attached metal bodies and a polymeric adhesive compound, illustrating the deflection and stoppage by the metal bodies of microcracks in the compound or at the compound-to-metal-carrier interface.

FIG. 5 shows schematically the flow of certain process steps of the method for fabricating a semiconductor device with enhanced thermal conductivity of the attachment layer as an embodiment of the invention.

FIG. 6 is a schematic cross section of a squeezed spheroid metal body, resembling a truncated cone, created by wire bonding technology as an embodiment of the computer-controlled methodology to fabricate customized array patterns of the metal bodies.

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Previous Patent Application:
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Next Patent Application:
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Industry Class:
Semiconductor device manufacturing: process
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stats Patent Info
Application #
US 20120094441 A1
Publish Date
Document #
File Date
Other USPTO Classes
438121, 257E21499
International Class

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