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Semiconductor device including a test circuit of a multivalued logic circuit having an impedance control

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Title: Semiconductor device including a test circuit of a multivalued logic circuit having an impedance control.
Abstract: A semiconductor device, having an input terminal configured to receive a multi-valued input signal as input, the multi-valued input signal including a plurality of values, a multi-valued logic circuit that operates with a multi-valued function and output binary signals to an output section in response to the input signal that has been input to the input terminal, the output section having a number of nodes being one less than a number of the plurality of values of the multi-valued input signal, and an impedance control circuit that is connected to the input terminal and the output section, and changes a combined resistance value in response to the binary signals of the plurality of nodes to change a current which flows in the input terminal. ...


Browse recent Renesas Electronics Corporation patents - Kawasaki-shi, JP
Inventors: Yoshitomo NUMAGUCHI, Munehisa OKITA
USPTO Applicaton #: #20120086478 - Class: 327108 (USPTO) - 04/12/12 - Class 327 


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The Patent Description & Claims data below is from USPTO Patent Application 20120086478, Semiconductor device including a test circuit of a multivalued logic circuit having an impedance control.

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The present application is a Continuation application of U.S. patent application Ser. No. 12/659,286 filed on Dec. 16, 2009, which is based on Japanese Patent Application No. 2009-95331, filed on Feb. 27, 2009, the entire contents of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a test circuit of a multivalued logic circuit.

2. Background of the Invention

In the semiconductor device field, with the large-scaled system and the increasing number of logic gates to be mounted, the number of input/output terminals is also remarkably increased. However, the number of input/output terminals that can be mounted on the semiconductor device is limited by a package. For that reason, there is a case in which a larger package must be employed when the number of input/output terminals exceeds a mountable limit. Under the circumstances, a reduction in the number of input/output is executed by using the multivalued logic circuit. However, there is a need to provide the semiconductor device with a test-use output terminal, which leads to a problem on a reduction in the number of terminals. Further, the number of multivalued logics that can be dealt with in the individual multivalued logic circuits is increased, whereby a technique enabling the multivalued logic circuit to be efficiently tested is increasingly required.

As a test of the semiconductor device including the multivalued logic circuit, there is a threshold voltage test of the multivalued input terminal. JP-A-03-209181 has proposed a method for reducing the number of terminals to be used in a threshold voltage test.

First, a description will be given of the configuration of a semiconductor device discloses in JP-A-03-209181 with reference to FIG. 9. As shown in FIG. 9, an n-valued input terminal 1 is connected with (n−1) comparators C1 to Cn−1. The comparators C1 to Cn−1 are connected to an internal logic 3 and a threshold voltage test circuit 6, respectively. Output terminals 5 are connected to the internal logic 3, respectively, and an output terminal 7 is connected to the internal logic 3 or the threshold voltage test circuit 6 through an output mode selector switch 4. The respective comparators C1 to Cn−1 are set with threshold voltages different gradually such as V1<V2< . . . <Vn−1, respectively.

The operation of testing the semiconductor device shown in FIG. 9 will be described. First, in order to observe an output signal of the threshold voltage test circuit 6 by using the output terminal 7, the output mode selector switch 4 changes over to connect the threshold voltage test circuit 6 and the output terminal 7.

In that state, an input voltage of the n-valued input terminal 1 is sequentially raised from 0 volt, an output signal of the comparator C1 whose threshold voltage is V1 changes to “H” level from “L” level. When the input voltage is raised as it is, an output signal of the comparator C2 whose threshold voltage is V2 changes to “H” level from “L” level. This operation is sequentially repeated with the results that an output signal of the comparator Cn−1 whose threshold voltage is Vn−1 finally changes to “H” level from “L” level.

In this situation, as shown in FIG. 10, a test output signal of the threshold voltage test circuit 6 is also inverted every time the output signals of the comparators C1 to Cn−1 are inverted. That is, an output signal observed at the output terminal is inverted when the input voltage of the n-valued input terminal 1 first reaches V1 volt, and again inverted when the input voltage then reaches V2 volt. This operation is repeated, and when the input voltage of the n-valued input terminal 1 reaches Vn−1 volt, (n−1)-th inversion is conducted.

Accordingly, when the voltage of the n-valued input terminal 1 when the test output signal is inverted is measured, and compared with the threshold voltages of the comparators C1 to Cn−1, it is possible to determine whether the comparators C1 to Cn−1 normally operate, or not.

The above description is applied to a case of typical n-valued input. A specific example of four-valued input will be described. FIG. 11 is a circuit configuration diagram showing the configuration of the threshold voltage test circuit 6 in the case of four-valued input. As shown in FIG. 11, the threshold voltage test circuit 6 includes two inversion logic blocks and three NAND logic blocks. The threshold voltage test circuit 6 is connected to the n-valued input terminal 1 through the comparators C1 to C3, and also to the output terminal 7. With the above configuration, the threshold voltage test circuit 6 sequentially generates inversion logic according to the output signals of the comparators C1 to C3, as shown in a characteristic diagram of FIG. 12.

SUMMARY

In the above-described semiconductor device, the test output signal from the threshold voltage test circuit 6 is observed by using the output terminal 7. Hence, the output mode selector switch 4 naturally required in the normal operation must be provided. That is, even in the normal operation, the output signal from the internal logic 3 is transmitted to the output terminal 7 via the output mode selector switch 4. Because this output signal, as compared with other output signals to be transmitted to the output terminal 5, passes through the output mode selector switch 4, there arises such a problem that a transmission delay occurs. As a result, the output signals from the output terminal 5 and the output terminal 7, which should be naturally synchronized with each other, are not synchronous with each other.

According to an aspect of the present invention, a semiconductor device includes: an input terminal to which an input signal is input; plural comparators that operate at different threshold voltages in response to the input signal that has been input to the input terminal, respectively; and an impedance control circuit that is connected to the input terminal and the outputs of the plural comparators, respectively, and changes a combined resistance value in response to output signals of the plural comparators, thereby changing a current which flows in the input terminal.

According to the present invention, since the operation of the comparators can be tested by only measuring a value of a current flowing in the input terminal to which the input signal is input, there is no need to newly provide an output terminal for observing the test output signal. Also, since there is no need to provide the output mode selector switch for outputting the test output signal by using the output terminal of the multivalued logic circuit, an increase in the transmission delay of the output signal of the multivalued logic circuit can be prevented.

According to the present invention, there can be provided the semiconductor device having the test circuit of the multivalued logic circuit without newly provision of the output terminal for the test signal, and with no increase in the transmission delay in the output signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit configuration diagram showing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a circuit configuration diagram showing an impedance control circuit according to the first embodiment of the present invention;

FIG. 3 is a circuit configuration diagram showing a semiconductor device according to a first example;

FIG. 4 is a circuit configuration diagram showing an impedance control circuit according to the first example;



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stats Patent Info
Application #
US 20120086478 A1
Publish Date
04/12/2012
Document #
13327003
File Date
12/15/2011
USPTO Class
327108
Other USPTO Classes
International Class
03K3/00
Drawings
11



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