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Method and system for modifying patterned photoresist using multi-step ion implantation / Varian Semiconductor Equipment Associates, Inc.




Title: Method and system for modifying patterned photoresist using multi-step ion implantation.
Abstract: A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality of ion exposure cycles are performed, wherein each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall, and providing ions at a tilt angle of about five degrees or larger upon the second sidewall. Upon the performing of the plurality of ion exposure cycles the mid frequency and low frequency linewidth roughness are reduced. ...


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USPTO Applicaton #: #20120083136
Inventors: Ludovic Godet, Joseph C. Olson, Patrick M. Martin


The Patent Description & Claims data below is from USPTO Patent Application 20120083136, Method and system for modifying patterned photoresist using multi-step ion implantation.

BACKGROUND

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OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to the field of semiconductor device manufacturing. More particularly, the present invention relates to a method, system and structure for patterning a substrate and for implanting into a substrate for manufacturing a semiconductor device.

2. Discussion of Related Art

With continuing miniaturization of electronic devices, there is an increased need for a patterning process capable of achieving finer resolution. Scaling, the ability to print smaller and smaller features, enables the desired design attributes of smaller more complex chips per wafer. Unfortunately, limitations in lithography process equipment can no longer keep up with device scaling requirements. Two key areas stand out in fine feature imaging; the first is a negative attribute referred to as Line Edge or Width Roughness (LER or LWR respectively) and the second is the lack of ability to print tight geometry due to diffraction limits. During the etch step (pattern transfer), the LER roughness from the PR is transferred to the material being etched. LER results in device degradation usually in transistor or parametric stability during testing. Instead of a smooth well defined photoresist image, the patterning process results in a very rough line edge. Depending on the design, either short, medium or long range roughness will have more of an impact on device performance. Since photolithography alone does not produce smooth lines, subsequent steps need to be developed to eliminate or reduce the edge roughness of the lines. To address this problem, several additional processes have been tried yielding only marginal results. For example, dry chemical etch processes have the ability to remove material from the resist image but they suffer pattern dependent loading effects from different exposed areas isolated to dense biases.

In addition, the resist critical dimension (CD) is typically required to be within a tight tolerance, such that any secondary technique should maintain the original resist attributes for profile, height, and CD. Dry chemical etch systems could also impart unwanted defects to the pattern which could result in yield loss. Another alternative approach is the use of a Deep Ultraviolet (DUV) cure where the rough resist pattern is exposed to a lamp based platform to heat the resist through radiation exposure which can smooth the lines. The drawback to this technique is that, after exposure, the corner of the line segments exhibit pattern pull back, and resist lines may deform in such a way to render subsequently produced devices useless. Moreover none of the aforementioned approaches has been observed to reduce low frequency roughness, which may play a large role in degradation of devices, especially those having small CD such as, for example, CD below 100 nm. Accordingly, it will be appreciated that there is a need to improve resist patterning processes for technologies requiring very small feature sizes, such as sub-100 nm CD devices.

SUMMARY

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OF THE INVENTION

Embodiments of the present invention are directed to methods and systems for patterning a substrate. One embodiment comprises a method of reducing the roughness profile in a plurality of patterned resist features, wherein each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall. The method includes performing a plurality of ion exposure cycles to reduce the roughness profile of a resist feature. Each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall and providing ions at a tilt angle of about five degrees or larger upon the second sidewall.

Another embodiment involves a method of reducing the roughness profile in a plurality of patterned resist features provided on a first surface of a substrate, wherein each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall. The method comprises providing the plurality of patterned resist features with a total ion dose by exposing, in a first exposure, the first surface of the substrate to a first ion dose at a first tilt angle that is greater than about five degrees from a substrate normal, wherein the first ion dose impinges on the first sidewall of the plurality of resist features. The first surface of the substrate is exposed, in a second exposure, to a second ion dose at a second tilt angle that is greater than about five degrees from a substrate normal, wherein the second ion dose impinges on the second sidewall of the plurality of resist features. The first surface of the substrate is exposed, in a third exposure, to a third ion dose at a third tilt angle that is greater than about five degrees from a substrate normal, wherein the third ion dose impinges on the first sidewall of the plurality of resist features. The first surface of the substrate is exposed, in a fourth exposure, to a fourth ion dose at a fourth tilt angle that is greater than about five degrees from a substrate normal, wherein the fourth ion dose impinges on the second sidewall of the plurality of resist features, wherein a total exposure dose is equivalent to the sum of the first, second, third and fourth ion doses.

Another embodiment comprises a system for reducing roughness in patterned resist features disposed on a substrate, where each resist feature has a first sidewall and second sidewall opposite the first sidewall. The system includes an ion source operable to provide an ion beam toward the substrate. The system also includes a substrate stage configured to provide a set of relative motions with respect to the ion beam, including a twist motion and a tilt motion. The system further includes a processor and a memory operable to store ion exposure parameters that comprise one or more of: a set of tilt angles, a set of twist angles, a set of ion energies, and a set of ion doses. The system also includes a computer-readable program operable in conjunction with the memory and the processor to send control signals to the ion source and to the substrate stage to perform a plurality of ion exposure cycles. Within each ion exposure cycle the substrate stage is oriented with respect to the ion beam so as to expose, at a tilt angle of about five degrees or larger, the first sidewall and second sidewall in an alternating fashion, to reduce a linewidth roughness profile associated with the patterned resist features.

BRIEF DESCRIPTION OF THE DRAWINGS

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FIG. 1 is a schematic of an ion implantation system.

FIG. 2a contains a schematic plan view of a patterned resist that illustrates general features of the invention.

FIG. 2b contains a schematic cross-sectional view of a patterned resist that illustrates general features of the invention.

FIG. 2c is a schematic depiction of resist linewidth roughness components.

FIGS. 3a-3e are schematic cross-sectional depictions of resist structures that illustrate steps involved in an exemplary multistep ion implantation process.

FIGS. 4a-4e illustrate another exemplary multistep ion implantation process.

FIGS. 5a-5e illustrate a further exemplary multistep ion implantation process.

FIG. 6 is a graph that depicts details of a multistep ion implantation processes.

FIG. 7 is a graph that depicts results of LWR and EWR measurements for resist samples subjected to the multistep ion implantation processes of FIG. 6.

FIG. 8 is a graph that shows the power spectrum distribution of LWR before and after exposure to ions for the multistep ion implantation processes of FIG. 6.

DESCRIPTION OF EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, like numbers refer to like elements throughout.

To solve the deficiencies associated with the methods noted above, novel and inventive techniques for improving roughness in patterned photoresist features are disclosed herein. Embodiments of the present invention relate to providing ions to a patterned resist that has a plurality of photoresist features. Photoresist features are subjected to a series of doses (exposures) of ions in which each sidewall of a photoresist feature is subject to a plurality of ion beam exposures (doses) from ion beams incident at a non-normal angle with respect to a substrate. In this manner, the LER, LWR, and medium and long scale roughness are improved for patterned photoresist features, as set forth in detail below.

In a preferred configuration of the invention, ions are provided to a substrate in an ion implantation system. Referring to the drawings, FIG. 1 is a block diagram of an ion implanter that illustrates general features of ion implanters that may be used in embodiments of the present invention. System 100 includes an ion source chamber 102. A power supply 101 supplies the required energy to source 102 which is configured to generate ions of a particular species. The generated ions are extracted from the source through a series of electrodes 104 (extraction electrodes) and formed into a beam 95 which passes through a mass analyzer magnet 106. The mass analyzer is configured with a particular magnetic field such that only the ions with a desired mass-to-charge ratio are able to travel through the analyzer. Ions of the desired species pass through deceleration stage 108 to corrector magnet 110. Corrector magnet 110 is energized to deflect ion beamlets in accordance with the strength and direction of the applied magnetic field to provide a beam targeted toward a work piece or substrate positioned on support (e.g. platen) 114. In some cases, a second deceleration stage 112 may be disposed between corrector magnet 110 and support 114. The ions lose energy when they collide with electrons and nuclei in the substrate and come to rest at a desired depth within the substrate based on the acceleration energy.

In accordance with embodiments of the present invention, the substrate may be attached to a movable stage configured to provide a set of relative motions with respect to a beam, such as beam 95. This may include a translational motion, a twist motion, and a tilt motion. The implantation system 100 includes a tilt stage that provides a substrate tilt with respect to an incident beam, for example, from about −75 to +75 degrees with respect to a normal to the substrate.

FIGS. 2a and 2b illustrate general features of a method of the present invention. Included in FIGS. 2a and 2b are schematic depictions of a conventional patterned resist 202 disposed on a substrate 200, shown in plan view, and cross-section, respectively. The patterned resist includes a plurality of lines 204 that are formed after a lithography process is applied to a layer of photoresist. As shown, the linewidth, which is measured in the direction ‘x,’ varies along the length L of each line 204. Using known lithography processes, the linewidth roughness (LWR) may be a significant fraction of the nominal linewidth especially in resist patterns where the critical dimension is less than about 100 nm. The resist lines 204 may have a nominal CD (W), which is depicted to be the same for the lines shown. As will be readily appreciated by those of skill in the art, if resist lines having a significant linewidth roughness (LWR), adjacent resist lines may have significantly different actual widths due to this linewidth roughness. However, adjacent lines 204 are depicted as similar in dimension for the purposes of explanation and clarity.

In addition to LWR, a “roughness profile” for the resist may include the line edge roughness (LER), as well as the short, medium, and long range LWR variation, which parameters correspond to different length scales along direction L over which linewidth variations occur. In addition to the absolute value of LWR or LER, the length scale over which such variations occur may be a key concern for device fabrication. For example, it is known that long range roughness in photoresist lines may have a different impact than short range roughness on device performance for devices patterned from the photoresist lines.

FIG. 2c illustrates how low frequency (204a), mid frequency (204b) and high frequency (204c) roughness components are obtained from a line 204. These components correspond to the long range, mid range, and short range roughness variations.

In embodiments of the present invention, a patterned resist, such as resist 202, is subjected to a series of ion doses (exposures), resulting in an improvement in the resist roughness profile after the series of exposures. The improvement (or reduction) in roughness profile denotes a reduction in one or of the following: LWR, EWR, and short, medium, or long range roughness variation. The present inventors have discovered that improvements in LWR can be optimized by controlling parameters associated with exposure to ions. These parameters may include, among others, angle(s) of incidence of ions, ion energy, ion type, total ion dose, and the specific sequence of a series of ion exposures, as detailed below.

In accordance with this invention, ions provided to substrate 200 may be incident at a non-zero tilt angle θ with respect to a normal N to the substrate plane, as illustrated in FIG. 2b for ion beams 218, 220, 222, and 224. In embodiments of the invention detailed below, a substrate, such as substrate 200 may be subjected to an ion beam in a series of exposure cycles. Each exposure cycle contains an exposure when the ion beam forms a positive tilt angle and an exposure when the ion beam forms a negative tilt angle. The alternating tilt angles used in each exposure cycle may range from about +/−5 degrees to about +/−85 degrees. Because the ion beam is incident at a non-zero tilt angle with respect to normal, ions may impact sidewalls of resist features and thereby more effectively attack roughness in the resist features.

As illustrated in FIG. 2a, the twist angle φ may also vary, as shown for ion beams 212, 214, and 216, preferably between about zero and about +/−15 degrees. For ion implantation of crystalline silicon wafers, the twist angle is generally defined as the angle formed between the plane that contains the ion beam and the wafer normal and the plane that is perpendicular to a primary flat, which is aligned along the direction in <100> Si. However, as used herein, the term “twist angle” refers to the angle formed between the plane that contains the ion beam and the wafer normal and the plane P that is perpendicular to the long axis L of the patterned resist feature, as illustrated in FIG. 2a. Accordingly, a zero twist angle indicates that the ion beam is in a plane perpendicular to the long axis of the resist lines, regardless of orientation of the underlying wafer.




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stats Patent Info
Application #
US 20120083136 A1
Publish Date
04/05/2012
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
/
Drawings
0




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Varian Semiconductor Equipment Associates, Inc.


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20120405|20120083136|modifying patterned photoresist using multi-step ion implantation|A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality |Varian-Semiconductor-Equipment-Associates-Inc
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