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Method and system for modifying patterned photoresist using multi-step ion implantation

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Title: Method and system for modifying patterned photoresist using multi-step ion implantation.
Abstract: A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality of ion exposure cycles are performed, wherein each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall, and providing ions at a tilt angle of about five degrees or larger upon the second sidewall. Upon the performing of the plurality of ion exposure cycles the mid frequency and low frequency linewidth roughness are reduced. ...


Browse recent Varian Semiconductor Equipment Associates, Inc. patents - Gloucester, MA, US
Inventors: Ludovic Godet, Joseph C. Olson, Patrick M. Martin
USPTO Applicaton #: #20120083136 - Class: 438798 (USPTO) - 04/05/12 - Class 438 
Semiconductor Device Manufacturing: Process > Radiation Or Energy Treatment Modifying Properties Of Semiconductor Region Of Substrate (e.g., Thermal, Corpuscular, Electromagnetic, Etc.) >Ionized Irradiation (e.g., Corpuscular Or Plasma Treatment, Etc.)

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The Patent Description & Claims data below is from USPTO Patent Application 20120083136, Method and system for modifying patterned photoresist using multi-step ion implantation.

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BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to the field of semiconductor device manufacturing. More particularly, the present invention relates to a method, system and structure for patterning a substrate and for implanting into a substrate for manufacturing a semiconductor device.

2. Discussion of Related Art

With continuing miniaturization of electronic devices, there is an increased need for a patterning process capable of achieving finer resolution. Scaling, the ability to print smaller and smaller features, enables the desired design attributes of smaller more complex chips per wafer. Unfortunately, limitations in lithography process equipment can no longer keep up with device scaling requirements. Two key areas stand out in fine feature imaging; the first is a negative attribute referred to as Line Edge or Width Roughness (LER or LWR respectively) and the second is the lack of ability to print tight geometry due to diffraction limits. During the etch step (pattern transfer), the LER roughness from the PR is transferred to the material being etched. LER results in device degradation usually in transistor or parametric stability during testing. Instead of a smooth well defined photoresist image, the patterning process results in a very rough line edge. Depending on the design, either short, medium or long range roughness will have more of an impact on device performance. Since photolithography alone does not produce smooth lines, subsequent steps need to be developed to eliminate or reduce the edge roughness of the lines. To address this problem, several additional processes have been tried yielding only marginal results. For example, dry chemical etch processes have the ability to remove material from the resist image but they suffer pattern dependent loading effects from different exposed areas isolated to dense biases.

In addition, the resist critical dimension (CD) is typically required to be within a tight tolerance, such that any secondary technique should maintain the original resist attributes for profile, height, and CD. Dry chemical etch systems could also impart unwanted defects to the pattern which could result in yield loss. Another alternative approach is the use of a Deep Ultraviolet (DUV) cure where the rough resist pattern is exposed to a lamp based platform to heat the resist through radiation exposure which can smooth the lines. The drawback to this technique is that, after exposure, the corner of the line segments exhibit pattern pull back, and resist lines may deform in such a way to render subsequently produced devices useless. Moreover none of the aforementioned approaches has been observed to reduce low frequency roughness, which may play a large role in degradation of devices, especially those having small CD such as, for example, CD below 100 nm. Accordingly, it will be appreciated that there is a need to improve resist patterning processes for technologies requiring very small feature sizes, such as sub-100 nm CD devices.

SUMMARY

OF THE INVENTION

Embodiments of the present invention are directed to methods and systems for patterning a substrate. One embodiment comprises a method of reducing the roughness profile in a plurality of patterned resist features, wherein each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall. The method includes performing a plurality of ion exposure cycles to reduce the roughness profile of a resist feature. Each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall and providing ions at a tilt angle of about five degrees or larger upon the second sidewall.

Another embodiment involves a method of reducing the roughness profile in a plurality of patterned resist features provided on a first surface of a substrate, wherein each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall. The method comprises providing the plurality of patterned resist features with a total ion dose by exposing, in a first exposure, the first surface of the substrate to a first ion dose at a first tilt angle that is greater than about five degrees from a substrate normal, wherein the first ion dose impinges on the first sidewall of the plurality of resist features. The first surface of the substrate is exposed, in a second exposure, to a second ion dose at a second tilt angle that is greater than about five degrees from a substrate normal, wherein the second ion dose impinges on the second sidewall of the plurality of resist features. The first surface of the substrate is exposed, in a third exposure, to a third ion dose at a third tilt angle that is greater than about five degrees from a substrate normal, wherein the third ion dose impinges on the first sidewall of the plurality of resist features. The first surface of the substrate is exposed, in a fourth exposure, to a fourth ion dose at a fourth tilt angle that is greater than about five degrees from a substrate normal, wherein the fourth ion dose impinges on the second sidewall of the plurality of resist features, wherein a total exposure dose is equivalent to the sum of the first, second, third and fourth ion doses.

Another embodiment comprises a system for reducing roughness in patterned resist features disposed on a substrate, where each resist feature has a first sidewall and second sidewall opposite the first sidewall. The system includes an ion source operable to provide an ion beam toward the substrate. The system also includes a substrate stage configured to provide a set of relative motions with respect to the ion beam, including a twist motion and a tilt motion. The system further includes a processor and a memory operable to store ion exposure parameters that comprise one or more of: a set of tilt angles, a set of twist angles, a set of ion energies, and a set of ion doses. The system also includes a computer-readable program operable in conjunction with the memory and the processor to send control signals to the ion source and to the substrate stage to perform a plurality of ion exposure cycles. Within each ion exposure cycle the substrate stage is oriented with respect to the ion beam so as to expose, at a tilt angle of about five degrees or larger, the first sidewall and second sidewall in an alternating fashion, to reduce a linewidth roughness profile associated with the patterned resist features.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of an ion implantation system.

FIG. 2a contains a schematic plan view of a patterned resist that illustrates general features of the invention.

FIG. 2b contains a schematic cross-sectional view of a patterned resist that illustrates general features of the invention.

FIG. 2c is a schematic depiction of resist linewidth roughness components.

FIGS. 3a-3e are schematic cross-sectional depictions of resist structures that illustrate steps involved in an exemplary multistep ion implantation process.

FIGS. 4a-4e illustrate another exemplary multistep ion implantation process.

FIGS. 5a-5e illustrate a further exemplary multistep ion implantation process.

FIG. 6 is a graph that depicts details of a multistep ion implantation processes.

FIG. 7 is a graph that depicts results of LWR and EWR measurements for resist samples subjected to the multistep ion implantation processes of FIG. 6.

FIG. 8 is a graph that shows the power spectrum distribution of LWR before and after exposure to ions for the multistep ion implantation processes of FIG. 6.

DESCRIPTION OF EMBODIMENTS

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stats Patent Info
Application #
US 20120083136 A1
Publish Date
04/05/2012
Document #
12896046
File Date
10/01/2010
USPTO Class
438798
Other USPTO Classes
25049221, 257E21328
International Class
/
Drawings
9



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