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Thermal warp compensation ic package

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Title: Thermal warp compensation ic package.
Abstract: An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art. ...


Browse recent Alcatel-lucent Canada Inc. patents - Ottawa, CA
Inventors: Paul James BROWN, Alex L. Chan
USPTO Applicaton #: #20120081872 - Class: 361783 (USPTO) - 04/05/12 - Class 361 


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The Patent Description & Claims data below is from USPTO Patent Application 20120081872, Thermal warp compensation ic package.

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FIELD OF THE INVENTION

The invention relates to warping of integrated circuit (IC) packages during manufacturing processing and is particularly concerned with providing a means for generally neutralizing the warpage by use of a counter-warping element.

BACKGROUND OF THE INVENTION

A wide variety of semiconductor packages having integrated circuits (IC) are used in industry. In general, ICs and their packages have been becoming more complex over time, with the result that their power, speed and their size has been increasing. With increased size and complexity also arise an increased number of connections from the integrated circuit to the larger electronics assembly of which it is a part. Historically, pin counts of Very Large Scale Integrated (VLSI) circuits exceeded the limits for dual in-line packaging (DIPs), leading to development of the Pin Grid Array (PGA). In the PGA the inputs and outputs of the integrated circuit are connected to an integrated circuit package in which pins are arranged in a square array that may cover up to the entire bottom of the package. The pins conduct electrical signals from the integrated circuit to the printed circuit board (PCB) in which or on which the IC package is mounted. A subsequent development to the PGA is that of the Ball Grid Array, or BGA, in with the pins are replaced by balls of solder affixed to the bottom of the integrated circuit package. During assembly to the printed circuit board, the BGA and printed circuit board are heated, causing the solder balls to melt and solder the integrated circuit package to the printed circuit board.

As the BGA packaging offers additional advantages, such as improved heat conduction due to the lower thermal resistance between the package and PCB, a lower inductance connection than pins, and reduced solder connection bridging; it has become a preferred packaging type.

One disadvantage of BGAs however, is the requirement for flatness during processing. In general, the solder connections require a tight mechanical tolerancing during processing in order to preclude mechanical stresses which would promote solder joint failure.

Working against this requirement, however, is the difference in thermal coefficient of expansion which exists between the substrate upon which the solder balls are mounted, and the silicon integrated circuit mounted upon the substrate. The differences in the thermal coefficient of expansion lead to warpage of the BGA package as a whole. This warpage, which for the purposes of this specification refers to a bending or twist or general lack of flatness in the overall integrated circuit package, including in particular the plane formed by the solder joint locations, can cause a variety of problems. A non-exhaustive list by way of example includes problems such as fractured solder joints, open contact solder joints, pillowed joints, or intermittent contact solder joints.

The problem of warpage is exacerbated by larger package sizes, and by elevated processing temperatures. As trends in integrated circuit complexity are consistently in the direction of larger package sizes, and as production changes in the direction of lead free solders yield higher processing temperatures, the problem of integrated circuit warpage is a pressing one. It is important to note that the desired tolerance for flatness at and across the processing temperature range can be very high. For example, for BGA packages having a size of greater than 1″ across, there may be a maximum warpage tolerance of on the order of 0.008″ allowed.

One prior solution to the problem of IC package warping has been the incorporation on top of the IC of a flat stiffener plate. The stiffener plate takes the form essentially of a completely flat entirely planar item having a constant thickness, and is a simple quadrilateral having approximately its perimeter as the size of the IC package perimeter when viewed from the top. A central region of the flat stiffener plate may be cut out in certain applications, for example to allow access of a thermally conductive element.

However, these stiffener flat plates suffer from the disadvantage that they themselves are entirely flat, and thus, have a somewhat limited resistance to warping due to temperature change or torsion or bending forces. In order to make a flat plate strong enough to provide desirable resistance to warping in the overall IC package, it can be necessary to make the stiffening plate undesirably thick. It is undesirable for the stiffening plate, which rests on top of the IC, to be too thick because the thick stiffening plate, on top of and added to the IC thickness, causes the entire assembled IC package to be thick, thus potentially limiting IC packaging placement options and/or increasing printed circuit card to printed circuit card separation in the final system assembly.

Further, the added stiffener thickness increases the IC die-to-lid spacing, thereby creating a larger separation that needs to be filled with thermal interface material, the longer thermal path ultimately impeding thermal dissipation from the IC. Moreover, because of the stiffener\'s entirely flat cross-sectional profile, increased stiffness is achieved inefficiently though the increase of the overall volume of material, thus adding additional cost and weight to the final IC package.

In view of the foregoing, it would be desirable to provide a means of decreasing warpage of IC packages. In particular, it would be desirable to provide a means that can provide improved performance and/or mounting reliability while providing a desirable low degree of thickness and/or a desirable low amount of material.

SUMMARY

OF THE INVENTION

It is an object of the invention to provide a temperature responsive warpage counteracting integrated circuit assembly.

According to an aspect of the invention there is provided a temperature responsive warpage counteracting integrated circuit assembly for use with an integrated circuit package having a connection grid side and a top side. The integrated circuit assembly has a first layer of a first material having a first coefficient of temperature expansion and a first and second surface; a second layer of a second material having a second coefficient of temperature expansion different from the first coefficient of temperature expansion and a first and second surface; the first surface of the second layer is bonded to the second surface of the first layer; and the second surface of the second layer is bonded to the top side of the integrated circuit package.

In some versions of this embodiment the first coefficient of temperature expansion is greater than the second coefficient of temperature expansion, while in other embodiments the second coefficient of temperature expansion is greater than the first coefficient of temperature expansion.

Advantageously, in some versions of this embodiment there may be apertures in the first and second layers, and in some versions these apertures are of a similar size and aligned.

Advantageously, in some versions the first layer may have a planar-convex cross-section with the planar portion at the second surface. In other versions of this embodiment the first layer may have a planar-concave cross-section with the planar portion at the second surface.

In another embodiment of the invention there is provided a temperature responsive warpage counteracting integrated circuit assembly for use with an integrated circuit package having a connection grid side and a top side. The integrated circuit assembly has a layer of a material having a coefficient of temperature expansion that varies from a first value at a first surface to a second value at a second surface; and the second surface of the layer of material is bonded to the top side of the integrated circuit package. In some versions of this embodiment the first value is larger than the second value, while in other versions the second value is larger than the first value.

Advantageously, in some versions of this embodiment the layer has an aperture therein. Also advantageously, in some versions of this embodiment the layer has a planar-convex or planar-concave cross-section with the planar portion being at the surface bonded to the integrated circuit package.

In another embodiment of the invention there is provided a method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly for use with an integrated circuit package having a connection grid side and a top side. The method has the steps of providing a first layer of a first material having a first coefficient of temperature expansion and a first and second surface; providing a second layer of a second material having a second coefficient of temperature expansion different from the first coefficient of temperature expansion and a first and second surface; bonding the first surface of the second layer to the second surface of the first layer; and bonding the second surface of second layer to the top side of the integrated circuit package.

In some versions of this embodiment, there is the step of providing that the first coefficient of temperature expansion is greater than the second coefficient of temperature expansion. In other versions of this embodiment there is the step of providing that the second coefficient of temperature expansion is greater than said the coefficient of temperature expansion.

Advantageously, in some versions of this embodiment there are the additional steps of providing a first aperture in the first layer; and providing a second aperture in the second layer, wherein the second aperture is of generally the same size as the first aperture, and aligned with the first aperture.

In yet another embodiment of the invention there is provided a method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly for use with an integrated circuit package having a connection grid side and a top side, the method having the steps of providing a layer of a material having a coefficient of temperature expansion that varies from a first value at a first surface to a second value at a second surface; and bonding the second surface of the layer of material to the top side of the integrated circuit package. In some versions of this embodiment there is the step of providing that the first value is greater than the second value. In other versions of this embodiment there is the step of providing that the second value is greater than the first value.

Advantageously, in some versions of this embodiment there is the additional step of providing an aperture in the layer of material.

Note: in the following the description and drawings that follow merely illustrate the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be further understood from the following detailed description of embodiments of the invention, with reference to the drawings in which:

FIG. 1a illustrates a cross-sectional drawing of an integrated circuit package which in accordance with the prior art;

FIG. 1b illustrates a cross-sectional drawing of the integrated circuit package of FIG. 1a which is showing a concave warpage due to elevated temperature;

FIG. 1c illustrates an exploded cross-sectional drawing of an integrated circuit package and a warpage compensation element in accordance with an embodiment of the present invention;

FIG. 1d illustrates a cross-sectional drawing of the integrated circuit package and the warpage compensation element of FIG. 1c bonded together in accordance with an embodiment of the present invention;

FIG. 2a illustrates another cross-sectional drawing of an integrated circuit package in accordance with the prior art;

FIG. 2b illustrates a cross-sectional drawing of the integrated circuit package of FIG. 2a which is showing a convex warpage due to elevated temperature;

FIG. 2c illustrates an exploded cross-sectional drawing of an integrated circuit package and a warpage compensation element in accordance with another embodiment of the present invention;

FIG. 2d illustrates a cross-sectional drawing of the integrated circuit package and warpage compensation element of FIG. 2c bonded together in accordance with an embodiment of the present invention;

FIG. 3a illustrates an isometric drawing of an integrated circuit package in accordance with the prior art; and

FIG. 3b illustrates an isometric drawing of the integrated circuit package of FIG. 3a with a warpage compensation element bonded thereto where the warpage compensation element has an aperture.

In the following figures, like features bear similar reference labels.

DETAILED DESCRIPTION

Referring now to the drawings, in which like numerals refer to like components or steps, there are disclosed broad aspects of various exemplary embodiments.

Many embodiments relate to a warpage reducing element that can be attached to an integrated circuit (IC) package. As used throughout this document, the terms IC (integrated circuit) and IC packaging are used interchangeably to make reference to the overall component assembly, which is also commonly referred to as the IC package. Examples of IC packages include for example TSOPS, QFPs, SOIC, BGA, CCGA, etc. It is noted that for packages containing above approximately 400 connections, IC packaging almost exclusively take on the form of Area Array style packaging, which itself can include various subtypes, such as for example Column Grid Arrays (CCGA), Pin Grid Arrays (PGA), and Ball Grid Arrays (BGA). The stiffener solutions that are described herein are applicable to such Area Array devices, including for example BGAs. The term IC assembly is used herein to refer to an IC or IC package that has a warpage reducing element incorporated therein or mounted thereto.

When referring herein to a plane, the reference includes the concept of a flat plate, which actually has a top and bottom flat surface and some thickness, with the top and bottom flat surfaces technically lying along parallel planes. Planar herein includes the concept of a plate being planar although it has such a thickness. Additionally, when referring herein to a planar-convex cross-section, the reference includes the concept of a plate having a flat bottom and a convex top surface. Likewise, when referring herein to a planar-concave cross-section, the reference includes the concept of a plate having a flat bottom and a concave top surface.

Referring to FIG. 1a there may be seen an integrated circuit 12 with a plurality of solder bumps 14. The solder bumps are for making connections to pads at a mounting location, for example on a printed circuit board.

Referring to FIG. 1b there may be seen the integrated circuit 12 with an exaggerated depiction of the warpage effect of a high temperature. Such a high temperature may occur during processing, for example when the integrated circuit is being mounted on a printed circuit board. In the case of processing with lead free solders, this high temperature may be on the order of 260° C. In this case the resulting warpage is concave in nature. The warpage generally results from a mismatch between the thermal coefficient of expansion of the silicon integrated circuit die and the thermal coefficient of expansion of the IC carrier to which the silicon die is affixed.

Referring to FIG. 1c there may be seen an integrated circuit 22. Also depicted is an assembly of materials having a first layer 26 and a second layer 28. Layers 26 and 28 are bonded together over their cojoined surfaces. In FIG. 1c, first layer 26 has a thermal coefficient of expansion which is larger than the thermal coefficient of expansion of second layer 28. Due to the differences in their respective thermal coefficient of expansion, a positive change in temperature will result in a greater degree of expansion of layer 26 than of cojoined layer 28. The net result of this greater degree of expansion, coupled with the cojoining of the layers is to induce a warpage in the combined layers which is opposite in nature to the warpage of the integrated circuit 12 in FIG. 1b.

Referring to FIG. 1d there may be seen the resulting temperature responsive warpage counteracting integrated circuit assembly wherein layer 28 is bonded to the surface of integrated circuit 22. This bonding may be effected by appropriate adhesives.

Alternatively, according to another embodiment of the invention, layer 28 may be built up via plating the surface of integrated circuit 22, and layer 26 established by plating the surface of layer 28.

Alternatively, according to yet another embodiment of the invention, layer 28 may be built up via plating the surface of integrated circuit 22, and layer 26 bonded to the surface of layer 28 by an appropriate adhesive.

Referring now to FIG. 2a there may be seen an integrated circuit 212 with a plurality of solder bumps 214. As previously described, the solder bumps are for making connections to pads at a mounting location, for example on a printed circuit board.

Referring to FIG. 2b there may be seen the integrated circuit 212 with an exaggerated depiction of the warpage effect of a high temperature. In this case the resulting warpage is convex in nature. This warpage generally results where the mismatch between the thermal coefficient of expansion of the silicon integrated circuit die and the thermal coefficient of expansion of the IC carrier to which the silicon die is affixed is opposite in nature to the situation depicted in FIG. 1b.

Referring to FIG. 2c there may be seen an integrated circuit 222. Also depicted is an assembly of materials having a first layer 228 and a second layer 226. Layers 228 and 226 are bonded together over their cojoined surfaces. In FIG. 2c, first layer 228 has a thermal coefficient of expansion which is smaller than the thermal coefficient of expansion of second layer 226. Due to the differences in their respective thermal coefficient of expansion, a positive change in temperature will result in a greater degree of expansion of layer 226 than of cojoined layer 228. The net result of this greater degree of expansion, coupled with the cojoining of the layers is to induce a warpage in the combined layers which is opposite in nature to the warpage of the integrated circuit 212 in FIG. 2b.



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stats Patent Info
Application #
US 20120081872 A1
Publish Date
04/05/2012
Document #
12895158
File Date
09/30/2010
USPTO Class
361783
Other USPTO Classes
438106, 257E21499
International Class
/
Drawings
4



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