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Ramp-stack chip package with static bends




Title: Ramp-stack chip package with static bends.
Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication. ...


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USPTO Applicaton #: #20120056327
Inventors: John A. Harada, David C. Douglas, Robert J. Drost


The Patent Description & Claims data below is from USPTO Patent Application 20120056327, Ramp-stack chip package with static bends.




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stats Patent Info
Application #
US 20120056327 A1
Publish Date
03/08/2012
Document #
12874446
File Date
09/02/2010
USPTO Class
257773
Other USPTO Classes
257E23141
International Class
01L23/52
Drawings
7




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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)   Combined With Electrical Contact Or Lead   Of Specified Configuration  

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20120308|20120056327|ramp-stack chip package with static bends|A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and |Oracle-International-Corporation