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Ramp-stack chip package with static bends

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Title: Ramp-stack chip package with static bends.
Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication. ...


Oracle International Corporation - Browse recent Oracle patents - Redwood City, CA, US
Inventors: John A. Harada, David C. Douglas, Robert J. Drost
USPTO Applicaton #: #20120056327 - Class: 257773 (USPTO) - 03/08/12 - Class 257 
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead >Of Specified Configuration

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The Patent Description & Claims data below is from USPTO Patent Application 20120056327, Ramp-stack chip package with static bends.

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BACKGROUND

1. Field

The present disclosure generally relates to the design of a semiconductor chip package. More specifically, the present disclosure relates to a chip package which includes a group of chips arranged in a stack and a ramp component which is at an angle relative to the stack, and which communicates with the chips at end segments of the semiconductor dies that include static bends.

2. Related Art

Chip packages that include stacked semiconductor chips can provide significantly higher performance in comparison to conventional individually packaged chips that are connected to a printed circuit board. These chip packages also provide certain advantages, such as the ability: to use different processes on different chips in the stack, to combine higher density logic and memory, and to transfer data using less power. For example, a stack of chips that implements a dynamic random access memory (DRAM) can use a high-metal-layer-count, high-performance logic process in a base chip to implement input/output (I/O) and controller functions, and a set of lower metal-layer-count, DRAM-specialized processed chips can be used for the rest of the stack. In this way the combined set of chips may have better performance and lower cost than: a single chip that includes I/O and controller functions manufactured using the DRAM process; a single chip that includes memory circuits manufactured using a logic process; or a system constructed by attempting to use a single process to make both logic and memory physical structures.

It can, however, be difficult to obtain low-cost, high-performance (e.g., high-bandwidth) interconnections between the stacked semiconductor chips. For example, the semiconductor chips can be electrically coupled using wire bonds between exposed bond pads on surfaces in a stack of chips in which the chips are offset from one another to define a staircase of chip edges. But while these wire bonds can be implemented using low-cost assembly techniques, the resulting wire bonds typically have a low bandwidth.

In contrast, through-silicon vias (TSVs) typically have a higher bandwidth than wire bonds. In a TSV fabrication technique, chips are processed so that one or more of the metal layers on their active face are conductively connected to new pads on their back face. Then, chips are adhesively connected in a stack, so that the new pads on the back face of one chip make conductive contact with corresponding pads on the active face of an adjacent chip.

However, TSVs typically have a higher cost than wire bonds. This is because TSVs pass through the active silicon layer of a chip. As a consequence, a TSV occupies area that could have been used for transistors or wiring. This opportunity cost can be large. For example, if the TSV exclusion or keep-out diameter is 20 μm, and TSVs are placed on a 30-μm pitch, then approximately 45% of the silicon area is consumed by the TSVs. This roughly doubles the cost per area for any circuits in the chips in the stack. (In fact, the overhead is likely to be even larger because circuits are typically spread out to accommodate TSVs, which wastes more area.) In addition, fabricating TSVs usually entails additional processing operations, which also increases cost.

Hence, what is needed is a chip package that offers the advantages of stacked chips without the problems described above.

SUMMARY

One embodiment of the present disclosure provides a chip package. This chip package includes a set of semiconductor dies arranged in a vertical stack in a vertical direction, which is substantially perpendicular to a first semiconductor die in the vertical stack. Moreover, each semiconductor die, after the first semiconductor die, is offset in a horizontal direction by an offset value from an immediately preceding semiconductor die in the vertical stack, thereby defining a stepped terrace at one side of the vertical stack. Furthermore, a ramp component is electrically and rigidly mechanically coupled to the semiconductor dies. This ramp component is positioned on the one side of the vertical stack, and is approximately parallel to a direction along the stepped terrace, which is between the horizontal direction and the vertical direction. Additionally, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component.

Note that stress in each of the semiconductor dies associated with the bend may be less than a yield strength of the semiconductor die. Furthermore, a thickness of each of the semiconductor dies may be defined such that each of the semiconductor dies has a bending moment that facilitates the bend.

The ramp component may be electrically coupled to the semiconductor dies using a variety of techniques. For example, the ramp component may be soldered to each of the semiconductor dies, such as at the end segment of each of the semiconductor dies. Alternatively or additionally, the ramp component may be electrically coupled to the end segment of each of the semiconductor dies by microsprings and/or an anisotropic conductive film. Furthermore, in some embodiments the ramp component may electrically couple electrical signals between the ramp component and the end segment of each of the semiconductor dies using capacitively coupled proximity communication.

In some embodiments, the ramp component includes: an optical waveguide configured to convey an optical signal along the direction; and a set of optical coupling elements, where a given optical coupling component in the set of optical coupling components may optically couple the optical signal to the end segment of a given semiconductor die in the set of semiconductor dies. Note that the optically coupling may include optical proximity communication.

Moreover, a variety of techniques may be used to align components in the chip package. For example, a surface of the end segment of each of the semiconductor dies may include an etch pit and, for each of the etch pits in the semiconductor dies, the ramp component includes a corresponding etch pit. Furthermore, the chip package may include a set of balls, where a given ball in the set of balls mechanically couples the etch pit in the surface of the end segment and the corresponding etch pit in the ramp component.

Another embodiment provides an electronic device (such as a computer system) that includes the chip package.

Another embodiment provides a method for communicating a signal. During this method the signal is conveyed in the ramp component which is electrically and rigidly mechanically coupled to the set of semiconductor dies that are arranged in the vertical stack in the vertical direction. Note that the semiconductor dies are offset from each other in the horizontal direction, thereby defining the stepped terrace on one side of the vertical stack. Furthermore, the ramp component is positioned on the one side of the vertical stack approximately parallel to the direction along the stepped terrace, which is between the horizontal direction and the vertical direction. Then, the signal is coupled to a given semiconductor die in the set of semiconductor dies at an end segment of the given semiconductor die, where the given semiconductor die includes a static bend so that the end segment is parallel to the direction and is mechanically coupled to the ramp component.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram illustrating a side view of a chip package in accordance with an embodiment of the present disclosure.

FIG. 2 is a block diagram illustrating a top view of the chip package in FIG. 1 in accordance with an embodiment of the present disclosure.

FIG. 3 is a block diagram illustrating a side view of a chip package in accordance with an embodiment of the present disclosure.

FIG. 4 is a block diagram illustrating a side view of a chip package in accordance with an embodiment of the present disclosure.

FIG. 5 is a flow diagram illustrating a method for communicating a signal in the chip package in accordance with an embodiment of the present disclosure.

FIG. 6 is a block diagram illustrating an electronic device that includes the chip package in accordance with an embodiment of the present disclosure.



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stats Patent Info
Application #
US 20120056327 A1
Publish Date
03/08/2012
Document #
12874446
File Date
09/02/2010
USPTO Class
257773
Other USPTO Classes
257E23141
International Class
01L23/52
Drawings
7



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