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Semiconductor wafer, semiconductor device and method of fabricating the same

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Title: Semiconductor wafer, semiconductor device and method of fabricating the same.
Abstract: A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer. ...


Browse recent Kabushiki Kaisha Toshiba patents - Minato-ku, JP
Inventor: Satoshi INABA
USPTO Applicaton #: #20120009744 - Class: 438197 (USPTO) - 01/12/12 - Class 438 
Semiconductor Device Manufacturing: Process > Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions >Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.)

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The Patent Description & Claims data below is from USPTO Patent Application 20120009744, Semiconductor wafer, semiconductor device and method of fabricating the same.

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CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2007-218459, filed on Aug. 24, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND

In a structure of a fin-type FET (Field Effect Transistor) (hereinafter referred to as “FinFET”), it is possible to provide several channel plane directions by setting a crystal plane direction and a channel direction of a substrate. Furthermore, it is known that an optimal channel direction with respect to a crystal axis to improve carrier mobility is different between an n-type FinFET and a p-type FinFET. For example, in general, both of the n-type and p-type FinFETs are often configured so that a plane direction of a fin side surface is (100) and an axial direction of a channel region formed on the fin side surface is <110>, however, it has been known that the carrier mobility is improved by configuring the plane direction of the fin side surface to be (100) and the axial direction of the channel region formed on the fin side surface to be <100> for the n-type FinFET while configuring the plane direction of the fin side surface to be (110) and the axial direction of the channel region formed on the fin side surface to be <110> for the p-type FinFET.

A technique to form one conductivity type of FinFET inclined at 45° with respect to another conductivity type of FinFET around a height direction so as to make plane directions and channel directions of fin side surfaces of both n-type and p-type FinFETs to be directions which improve the carrier mobility as described above when mounting the n-type and p-type FinFETs together on a Si substrate of which plane direction of one principal surface is (100), is known. This technique, for example, is disclosed in a non-patent literary document of B. Doris et al., Symp. on VLSI Tech. Dig. of Tech. Papers, pp. 86-87, 2004.

Meanwhile, a technique, to give different crystal directions to an n-type and p-type device regions on the same substrate, in which semiconductor substrates having different plane directions are laminated, and then, a predetermined region of the upper substrate recrystallized so as to reflect a plane direction of the lower substrate after amorphizing the predetermined region of the upper substrate, is known. This technique, for example, is disclosed in U.S. Pat. No. 7,023,055.

BRIEF

SUMMARY

A semiconductor substrate according to one embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer.

A semiconductor device according to another embodiment includes: a semiconductor substrate; a first transistor formed on the semiconductor substrate and having a first fin; and a second transistor formed on the semiconductor substrate and having a second fin of which plane direction of the upper surface is identical to that of the first fin, a channel direction in the second fin with respect to a crystal axis of the side surface portion of the second fin being different from a channel direction in the first fin with respect to a crystal axis of the side surface portion of the first fin, and a direction in which the second fin is arranged being substantially parallel or vertical to a direction in which the first fin is arranged within a plane parallel to a surface of the semiconductor substrate.

A method of fabricating a semiconductor device according to another embodiment includes: laminating a second substrate, of which plane direction of the principal surface is same as that of a first substrate, on the first substrate in the state that the crystal-axis directions in the principal surfaces of the first and second substrates are at a predetermined angle around a direction vertical to the principal surface to each other, forming first and second fins by patterning the second substrate, selectively amorphizing the first fin; and substantially matching the crystal-axis direction of the unit cell of the first fin to that of the first substrate by recrystallizing the amorphized first fin using the first substrate as a base.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a semiconductor device according to a first embodiment;

FIG. 2 is a cross sectional view of the semiconductor device according to the first embodiment when a cut surface taken on line II-II of FIG. 1 is viewed in a direction indicated by an arrow in the figure;

FIG. 3 is a cross sectional view of the semiconductor device according to the first embodiment when a cut surface taken on line III-III of FIG. 1 is viewed in a direction indicated by an arrow in the figure;

FIGS. 4A to 4K are cross sectional views showing processes for fabricating the semiconductor device according to the first embodiment;

FIG. 5 is a cross sectional view of the semiconductor device according to a second embodiment;

FIGS. 6A to 6E are cross sectional views showing processes for fabricating the semiconductor device according to the second embodiment;

FIGS. 7A to 7C are cross sectional views showing processes for fabricating the semiconductor device according to a third embodiment; and

FIG. 8 is a cross sectional view of a semiconductor device according to a fourth embodiment.

DETAILED DESCRIPTION

First Embodiment

FIG. 1 is a perspective view of a semiconductor device according to a first embodiment. Furthermore, FIG. 2 is a cross sectional view when a cut surface taken on line II-II of FIG. 1 is viewed in a direction indicated by an arrow in the figure. Furthermore, FIG. 3 is across sectional view when a cut surface taken on line III-III of FIG. 1 is viewed in a direction indicated by an arrow in the figure.



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Semiconductor device manufacturing: process
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stats Patent Info
Application #
US 20120009744 A1
Publish Date
01/12/2012
Document #
13239848
File Date
09/22/2011
USPTO Class
438197
Other USPTO Classes
257E21567
International Class
01L21/762
Drawings
13



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