FreshPatents.com Logo
stats FreshPatents Stats
2 views for this patent on FreshPatents.com
2012: 2 views
Updated: August 03 2014
newTOP 200 Companies filing patents this week


    Free Services  

  • MONITOR KEYWORDS
  • Enter keywords & we'll notify you when a new patent matches your request (weekly update).

  • ORGANIZER
  • Save & organize patents so you can view them later.

  • RSS rss
  • Create custom RSS feeds. Track keywords without receiving email.

  • ARCHIVE
  • View the last few months of your Keyword emails.

  • COMPANY DIRECTORY
  • Patents sorted by company.

Follow us on Twitter
twitter icon@FreshPatents

Phase change memory coding

last patentdownload pdfimage previewnext patent


Title: Phase change memory coding.
Abstract: An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit. ...


Browse recent Macronix International Co., Ltd, patents - Hsinchu, TW
Inventors: HSIANG-LAN LUNG, Ming Hsiu Lee, Yen-Hao Shih, Tien-Yen Wang, Chao-I Wu
USPTO Applicaton #: #20110317480 - Class: 365163 (USPTO) - 12/29/11 - Class 365 


view organizer monitor keywords


The Patent Description & Claims data below is from USPTO Patent Application 20110317480, Phase change memory coding.

last patentpdficondownload pdfimage previewnext patent

PARTIES TO A RESEARCH AGREEMENT

International Business Machines Corporation, a New York corporation and Macronix International Corporation, Ltd., a Taiwan corporation, are parties to a Joint Research Agreement.

BACKGROUND

This invention relates to phase change memory devices.

Phase change based memory materials, such as chalcogenide-based materials and similar materials, can be caused to change phase between an amorphous phase and a crystalline phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous phase is characterized by higher electrical resistivity than the generally crystalline phase, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.

The change from the amorphous phase to the crystalline phase, referred to as set herein, is generally a lower current operation. Generally, a current pulse for a set operation has a magnitude that is not sufficient to melt the active region of a cell, but heats the active region to a transition temperature at which amorphous phase change material tends to change to a crystalline solid phase. The change from crystalline phase to amorphous phase, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure. The reset pulse generally has a short duration and quick fall time, so that the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in an amorphous solid phase. The magnitude of the current needed for reset can be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.

One limitation on applications of phase change memory arises from the fact that phase transitions are caused by heat. Thus, heat in an environment in which the chip is deployed can cause loss of data, and loss of reliability.

Also, this limitation to use in environments that do not expose the chips to heat creates another limitation on applications of the technology. Specifically, the chip may be mounted onto and electrically connected to circuitry in a substrate (such as a package substrate, or a printed circuit board, for example), in a surface mount operation or other mounting process that involves a thermal cycle. For example, the surface mount operation typically includes a solder reflow procedure, requiring that the assembly (including the chip) be heated to bring the solder to a temperature about the melting point (or the eutectic point) of the alloy constituting the solder. Other mounting procedures also involve thermal cycles subjecting the chip to high temperatures. This may result in a change in the resistance of the material in these cells, so that the cell is no longer read as programmed.

For this reason, prior art phase change memory chips have not been available that are capable of retaining a data set stored before the mounting process. So, board manufacturers are required to store any necessary code on the chip, after assembly of the circuit board or after assembly of a system including the circuit board. This makes phase change memory devices less desirable than other types of non-volatile memory for many uses.

It is desirable to provide a phase change memory chip that can be used in extreme operating environments. It is desirable to provide a phase change memory chip that can be coded prior to mounting on a circuit board, using a process that retains the data during thermal cycles encountered during board or assembly manufacturing.

SUMMARY

A phase change memory device described herein can hold data through thermal events, such as a mounting process involving soldering, and in high temperature environments.

An integrated circuit comprises an array of single bit, phase change memory cells, including a data set stored therein represented by some memory cells in the array having a first resistance state and by other memory cells in the array having a second resistance state. The first resistance state corresponds to a crystalline phase active region having a first temperature-hardened morphology, and the second resistance state having a minimum resistance provided by crystalline phase active region having a second morphology. As the term is used herein, morphology refers to the structure and stoichiometry of the memory material, which can change locally in response to applied energy at an active region of a memory element. Thus, the first temperature-hardened morphology and the second morphology differ by one or more of grain size, stoichiometry of the phase change material, concentration of additives, segregation of additives, or other characteristics that contribute to changes in resistance of the active region. The first temperature-hardened morphology is characterized by being induced by higher energy current pulses than the second morphology, being a crystalline phase and by holding a lower resistance than the second morphology under thermal stress that can cause phase transition from the amorphous phase to a crystalline phase in the phase change material of the cell. Also, the temperature-hardened morphology can have a structure that does not fall in resistance, and does not increase in resistance by more than a predetermined amount, in response to thermal events. The second morphology is characterized by being induced at lower energy, being a crystalline phase and maintaining a higher resistance than the first morphology under thermal stress that would cause phase transition from an amorphous phase to a crystalline phase in the phase change material of the cell.

The first morphology can be induced using a set pulse having relatively long duration and slow fall time, with a magnitude and duration to deliver an energy sufficient to cause the morphology change. The second morphology can be induced using a typical set pulse with a fall time allowing crystalline phase formation, while having an energy insufficient to cause the lower, first resistance state.

A method for operating a phase change memory is described based on inducing a lower resistance state in some cells in the memory, and a higher resistance state in some other cells in the memory, where the lower resistance state corresponds with the first morphology and the higher resistance state corresponds with the second morphology.

A method for manufacturing a circuit including an integrated circuit phase change memory with pre-coding is described, based on coding a data set in the integrated circuit phase change memory by inducing a lower resistance state in some cells and the memory, and a higher resistance state in some other cells in the memory. The process involves mounting the integrated circuit phase change memory on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the process involves reading the data set by sensing first and second resistance states, which correspond to the lower and higher resistance states after the thermal event of mounting the integrated circuit.

A process can be executed if desired for a particular application, to change cells in the first resistance state to a third resistance state and to change cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin even after a mounting process that involves solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit including the integrated circuit phase change memory. In support of this process, an integrated circuit is described that includes an array of phase change memory cells with sensing circuits operable in first and second modes. The first mode is used for sensing data values in the array in response to the first and second resistance states used for pre-coding. The second mode is used for sensing data values in the array in response to the third and fourth resistance states which are used during operation of the device. Control circuits and biasing circuits are coupled to the array, and arranged to execute transition processes for changing from the pre-coded resistance states to the operational mode resistance states. Processes include reading a data set with the sensing circuits in the first mode by sensing the first and second resistance states, changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state so that thereafter, the data set is readable with the sensing circuits in the second mode. Also, processes executed under control of the control circuits and biasing circuits include write processes to write data in the array by inducing the third and fourth resistance states in addressed cells, and read processes to read data in the array with the sensing circuits in the second mode. Prior to the transition processes, the integrated circuit can include a pre-coded data set represented by some memory cells in the array having the first resistance state, and by other memory cells in the array having a second resistance state.

Phase change materials as formed for use in an integrated circuit phase change memory have a basis stoichiometry. A process for inducing a lower resistance state in a memory cell as described herein includes applying a current pulse to cause a change in the stoichiometry in the active region of the cell, to a combination having a lower crystalline phase resistance than the crystalline phase resistance of the basis material. A pulse used to induce the lower resistance state can have a magnitude below the threshold for causing melting of the active region, with a duration long enough to allow stoichiometric changes in the active region. For example, where the basis phase change material comprises a dielectric-doped GexSbyTez, such as for example Ge2Sb2Te5, a lower resistance state can be induced by applying a current pulse cause a change in stoichiometry in the active region to a combination having an increased concentration of antimony Sb. It is found that the lower resistance state can have a lower resistance than the resistance of a similar cell having a stoichiometry closer to the basis stoichiometry, such as encountered by a cell which had not undergone the process of inducing the change. The term “stoichiometry” as used here refers to the quantitative relationship in atomic concentration between two or more substances in the phase change material in a volume measurable, for example, using energy dispersive x-ray spectroscopy (EDX), or equivalent techniques. Also, as explained above, the grain size of the lower resistance state can be larger, also contributing to the lower resistance of the cell.

The higher resistance state used in the pre-coding process can be induced using a typical set pulse have an energy insufficient to cause the lower, first resistance state. The higher resistance state used in the pre-coding process can be induced using a reset pulse having a fall time that prevents transition to a crystalline phase and thereby presents formation of the lower, first resistance state.

The third resistance state, into which cells pre-coded into the first resistance state are changed, can be a higher resistance state induced by applying a pulse to induce an amorphous phase in the active region of the cell. The fourth resistance state into which cells pre-coded into the second resistance state are changed, can be an intermediate resistance state induced by applying a pulse to induce a crystalline phase in the active region of the cell.

The technology described here enables use of phase change memory integrated circuit in systems that rely on non-volatile memory to store configuration data, computer programs and the like, typically implemented using NOR Flash devices, which can be pre-coded. Thus, phase change memory integrated circuits can be “designed in” to systems, without creating requirements for modifications of manufacturing lines to ensure that an embedded system can be programmed after the system is assembled, and without requiring the added expense of implementing such programming processes.

The temperature-hardened morphology described herein can also be used as a one-time programmable fuse for many integrated circuit applications, such as redundancy coding for memory arrays, chip signatures, chip option coding and so on.

The technology described here enables use of phase change memory integrated circuit in systems that are employed in more extreme environments.

Other aspects and advantages of the technology described here are set forth below with reference to the figures, the detailed description and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing stages in assembly of semiconductor chips onto a circuit board.

FIGS. 2A and 2B are diagrammatic sketches in sectional view showing stages in a surface mounting procedure.

FIG. 3 is a diagram illustrating a temperature schedule for a surface mounting procedure.

FIG. 4 is a simplified diagram of a cross-section of a phase change memory cell.

FIG. 5 is a simplified diagram of a cross-section of a phase change memory cell, like that of FIG. 4, in which the active region is in a low resistance state.

FIG. 6 is a diagram showing resistances of phase change material in memory cells at an initial state, at a state following a “set” procedure, and at a state following a “reset” procedure according to the prior art.

FIG. 7A is a graph of temperature versus time in an active region showing a general comparison for “set” “long set” and “reset” procedures according to an embodiment of the invention.

FIGS. 7B and 7C show representative current pulse shapes for normal set and long set operations, respectively.

FIGS. 7D-7L illustrate alternative pulse shapes for long set pulses.

FIG. 7M is a graph showing resistance drift due to thermal loading versus set pulse length.

FIGS. 8A-8D are diagrams showing resistance of phase change material in memory cells at various stages in a cell programming procedure according to an embodiment of the invention.

FIGS. 9A and 9B are diagrams showing a relationship of sense amplifier settings and cell resistances in first and second modes as described herein.

FIG. 10 is a diagram showing heuristically an effect on cell resistance of subjecting a chip to a thermal cycle after coding using the long set and set processes described herein.

FIG. 11 is an example of a sense amplifier circuit suitable for use in connection with a memory array according to an embodiment of the invention.

FIG. 12 is a simplified block diagram showing an integrated circuit including a PCM memory array with transitional and operational modes as described herein.

FIG. 13 is a flow chart showing a pre-mounting write process as described herein.

FIG. 14 is a flow chart showing a transition mode for post-mounting read followed by write process as described herein.

FIGS. 15-17 are simplified diagrams of cross-sections of alternative phase change memory cell configurations.

FIG. 18 is a simplified block diagram of a temperature-hardened phase change memory as described herein.

FIG. 19 is a graph of reset and set state resistance distributions after a 245° C. 1 hr baking for a test chip.

FIG. 20 is a graph of initial state resistance distributions before and after the 245° C. 1 hr baking for a test chip.

FIG. 21 is a graph of set state resistance distributions before and after the 245° C. 1 hr baking for a test chip.

FIG. 22 is a graph of strong set state and initial state resistance distributions before and after the 245° C. 1 hr baking.

FIG. 23 is a graph of strong set state and reset state resistance distributions after the 245° C. 1 hr baking

FIG. 24 is a graph of set and reset state resistance distributions of strong set cells after a 10 M cycling endurance test. The memory window is larger than one order of magnitude

DETAILED DESCRIPTION

The invention will now be described in further detail by reference to the drawings, which illustrate alternative specific embodiments and methods. The drawings are diagrammatic, showing features of the embodiments and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the figures illustrating various embodiments, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the figures. Also for clarity of presentation certain features are not shown in the figures, where not necessary for an understanding of the invention. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods and that the invention may be practiced using other features, elements, methods and embodiments. Particular embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows.



Download full PDF for full patent description/claims.

Advertise on FreshPatents.com - Rates & Info


You can also Monitor Keywords and Search for tracking patents relating to this Phase change memory coding patent application.
###
monitor keywords



Keyword Monitor How KEYWORD MONITOR works... a FREE service from FreshPatents
1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored.
3. Each week you receive an email with patent applications related to your keywords.  
Start now! - Receive info on patent apps like Phase change memory coding or other areas of interest.
###


Previous Patent Application:
Data programming circuits and memory programming methods
Next Patent Application:
Phase change memory word line driver
Industry Class:
Static information storage and retrieval
Thank you for viewing the Phase change memory coding patent info.
- - - Apple patents, Boeing patents, Google patents, IBM patents, Jabil patents, Coca Cola patents, Motorola patents

Results in 0.84272 seconds


Other interesting Freshpatents.com categories:
Computers:  Graphics I/O Processors Dyn. Storage Static Storage Printers

###

Data source: patent applications published in the public domain by the United States Patent and Trademark Office (USPTO). Information published here is for research/educational purposes only. FreshPatents is not affiliated with the USPTO, assignee companies, inventors, law firms or other assignees. Patent applications, documents and images may contain trademarks of the respective companies/authors. FreshPatents is not responsible for the accuracy, validity or otherwise contents of these public document patent application filings. When possible a complete PDF is provided, however, in some cases the presented document/images is an abstract or sampling of the full patent application for display purposes. FreshPatents.com Terms/Support
-g2-0.3166
     SHARE
  
           

FreshNews promo


stats Patent Info
Application #
US 20110317480 A1
Publish Date
12/29/2011
Document #
12823508
File Date
06/25/2010
USPTO Class
365163
Other USPTO Classes
438102, 365148, 36518915, 257E21068
International Class
/
Drawings
23



Follow us on Twitter
twitter icon@FreshPatents