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High voltage durability iii-nitride hemt

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Title: High voltage durability iii-nitride hemt.
Abstract: A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT. ...


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Inventor: Michael A. Briere
USPTO Applicaton #: #20110284869 - Class: 257 76 (USPTO) - 11/24/11 - Class 257 
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Specified Wide Band Gap (1.5ev) Semiconductor Material Other Than Gaasp Or Gaalas

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The Patent Description & Claims data below is from USPTO Patent Application 20110284869, High voltage durability iii-nitride hemt.

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The present application is a continuation-in-part of, and claims the benefit of and priority to a pending parent patent application entitled “III-Nitride Wafer and Devices Formed in a III-Nitride Wafer,” Ser. No. 12/324,119, filed on Nov. 26, 2008. The disclosure in that pending parent application is hereby incorporated fully by reference into the present application.

BACKGROUND OF THE INVENTION

Definition

In the present application, “group III-V semiconductor” refers to a compound semiconductor that includes at least one group III element and at least one group V element, such as, but not limited to, gallium nitride (GaN), gallium arsenide (GaAs), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN) and the like. Analogously, “III-nitride” refers to a compound semiconductor that includes nitrogen and at least one group III element such as, but not limited to, GaN, AlGaN, InN, AlN, InGaN, InAlGaN and the like.

I.

FIELD OF THE INVENTION

The present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of fabrication of compound semiconductors.

2.

BACKGROUND ART

Semiconductor based devices, circuits, and switches employed in various modern applications are often required to display greater power handling capabilities and tolerate higher applied voltages than ever before. One response to these increased device performance demands has been the development and implementation of III-nitride semiconductor devices, such as high electron mobility transistors (HEMTs). In a typical HEMT, for example, a two-dimensional electron gas (2DEG) is generated at a semiconductor heterojunction. The 2DEG represents a very thin conduction layer of highly mobile and highly concentrated charge carriers free to move readily in the two dimensions of that conduction layer, but constrained from movement in a third dimension perpendicular to the conduction layer.

In practice, the ability of a HEMT, or any III-nitride semiconductor device, to perform reliably in the face of a high applied voltage (e.g. voltage greater than 600 volts), depends in part on the charge retention characteristics of the 2DEG or other type of conduction channel. In particular, where charge carriers are insufficiently constrained from dispersing out of a desired conduction zone, for example by movement into a silicon substrate of the device, device performance may be less than optimal. More seriously, under applied voltages of even a few hundred volts, a HEMT may short through its silicon substrate, resulting in device failure. Unfortunately, conventional approaches to III-nitride semiconductor device fabrication have failed to provide optimal charge carrier constraint within the conduction zone when high voltage is applied.

Thus, there is a need to overcome the drawbacks and deficiencies in the art by providing a III-nitride semiconductor device, such as a HEMT, exhibiting high voltage durability. It would be of additional advantage if the proposed solution were to provide an implementation capable of supporting monolithic vertical integration of III-nitride power semiconductor devices and silicon devices.

SUMMARY

OF THE INVENTION

A high voltage durability III-nitride semiconductor device, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of a semiconductor wafer, according to one embodiment of the present invention.

FIG. 2 shows a cross-sectional view of a high voltage durability III-nitride semiconductor device, according to one embodiment of the present invention.

FIG. 3 shows a cross-sectional view of a high voltage durability III-nitride semiconductor device including an insulated gate, according to one embodiment of the present invention.

FIG. 4 shows a cross-sectional view of a high voltage durability III-nitride semiconductor device including a Schottky gate, according to one embodiment of the present invention.

FIG. 5 shows a cross-sectional view of an enhancement mode high voltage durability III-nitride semiconductor device including an insulated gate, according to one embodiment of the present invention.

FIG. 6 shows a cross-sectional view of an enhancement mode high voltage durability III-nitride semiconductor device including a Schottky gate, according to one embodiment of the present invention.

FIG. 7 shows a cross-sectional view of a depletion mode high voltage durability III-nitride semiconductor device including an insulated gate, according to one embodiment of the present invention.

FIG. 8 shows a cross-sectional view of a depletion mode high voltage durability III-nitride semiconductor device including a Schottky gate, according to one embodiment of the present invention.



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stats Patent Info
Application #
US 20110284869 A1
Publish Date
11/24/2011
Document #
13197676
File Date
08/03/2011
USPTO Class
257 76
Other USPTO Classes
257194, 257195, 257E29252, 257E29091, 257E27027
International Class
/
Drawings
5


Semiconductor Device
Silicon


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