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Phosphorus activated nmos using sic process   

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Abstract: A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure (114). Source and drain regions (140, 142) are then formed (26) within the semiconductor substrate (102) on opposing sides of the channel (122) with a phosphorus dopant. ...

Agent: Texas Instruments Incorporated - Dallas, TX, US
Inventors: Srinivasan Chakravarthi, P. R. Chidambaram
USPTO Applicaton #: #20110212584 - Class: 438197 (USPTO) - 09/01/11 - Class 438 
Related Terms: GATE   Gate   Phosphorus   Semiconductor Substrate   
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The Patent Description & Claims data below is from USPTO Patent Application 20110212584, Phosphorus activated nmos using sic process.

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Patent Applications in related categories:

20130122671 - Process to remove ni and pt residues for niptsi applications - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. ...

20130122670 - Process to remove ni and pt residues for niptsi applications using chlorine gas - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention ...


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Method for providing semiconductors having self-aligned ion implant
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Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof
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