Transmitter with internal compensation for variance in differential data line impedance   

In order for high-speed differential data communications to be successful, predetermined communication parameters need to be met. For example, the transmitter output impedance, the data line characteristic impedance, and the receiver input impedance should be matched to limit data reflections.

SUMMARY

In at least some embodiments, an electronic device comprises a first data endpoint and differential data transceiver coupled to the first data endpoint. The differential data transceiver providing a communication interface between the first data endpoint and a second data endpoint. The differential transceiver internally compensates for variations in a series impedance for a differential data line between the differential transceiver and the second data endpoint.

In at least some embodiments, a differential data transmitter comprises a differential data line port and programmable circuitry coupled to the differential data line port. The programmable circuitry internally compensates for external variances in a differential data line series impedance.

In at least some embodiments, a method is performed for a differential data transmitter. The method comprises detecting a variance in a differential data line series impedance and programming the differential data transmitter to internally compensate for the variance.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of various embodiments of the invention, reference will now be made to the accompanying drawings in which:

FIG. 1 shows a system in accordance with an embodiment of the disclosure;

FIG. 2 shows an embodiment of the programmable circuitry described for FIG. 1;

FIG. 3 shows a printed circuit board of an electronic device in accordance with an embodiment of the disclosure;

FIG. 4 illustrates waveform variations output by a differential data transmitter in accordance with an embodiment of the disclosure; and

FIG. 5 shows a method in accordance with an embodiment of the disclosure.

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, computer companies may refer to a component by different names. This document doe not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The term “system” refers to a collection of two or more hardware and/or software components, and may be used to refer to an electronic device or devices or a sub-system thereof.

DETAILED DESCRIPTION

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

Embodiments of the invention are directed to differential data transmitters and related systems and methods. In at least some embodiments, a differential data transmitter internally compensates for external variations in the series impedance of a differential data line coupled thereto. In this manner, predetermined requirements for differential data communications can be met while maintaining flexibility with external device components or circuitry that are desired or inherent for different product designs, but that affect the series impedance of the differential data line.

FIG. 1 shows a system 100 in accordance with an embodiment of the disclosure. As shown, the system 100 comprises a first electronic device 102 and a second electronic device 160 configured to communicate via a differential data line 130. More specifically, the first electronic device 102 comprises a differential data transceiver 104 coupled to a data endpoint 106. Similarly, the second electronic device 160 comprises a differential data transceiver 140 coupled to a data endpoint 150. Each of the data endpoints 106, 150 corresponds to an addressable component that is the source or sink of information transmitted between the first and second electronic devices 102, 160. As an example, each of the electronic devices 102, 160 may be a host device or a peripheral device compatible with the Universal Serial Bus (USB) 2.0 protocol or another differential data communication protocol.

As shown, the differential data transceiver 104 comprises a high-speed receiver 110 and a high-speed transmitter 108 coupled between the data endpoint 106 and the differential data line 130. In operation, the high-speed transmitter 108 receives data from the data endpoint 106 and controls the voltage levels on the differential data line 130 to transmit a representation of this data over the different data line 130. Meanwhile, the high-speed receiver 110 is configured to examine the voltage levels on the different data line 130 and to decode data accordingly. The decoded data is then forwarded to the data endpoint 106. If the first electronic device 102 has multiple data endpoints, as may be the case in some embodiments, the high-speed receiver 110 is be to forward the data to the correct data endpoint based on an addressing scheme. The operation of the differential data transceiver 140 and its components (e.g., the high-speed transmitter 144 and the high-speed receiver 142) can be understood to be similar to the operation of the differential data transceiver 104 and its components. However, at least one of the differential data transceivers 104, 160 comprises programmable circuitry that enables compensation for external variations in the series impedance of the differential data line 130. In FIG. 1, the differential data transceiver 104 is shown to have this programmable circuitry 120. However, such programmable circuit could additionally or alternatively be implemented with the differential data transceiver 140.

In accordance with at least some embodiments, the programmable circuitry 120 compensates for variations in the series impedance of the differential data line 130 by programming the resistance of single-ended termination resistors (ZTERM) 122 for the differential data line 130. Additionally or alternatively, the programmable circuitry 120 compensates for variations in the series impedance by varying a programmable transmitter output current drive. Additionally or alternatively, the programmable circuitry 120 compensates for variations in the series impedance by varying a programmable transient boost current. Additionally or alternatively, the programmable circuitry 120 compensates for variations in the parallel impedance by varying a programmable transient boost current. In accordance with at least some embodiments, the transient boost current opens an eye diagram during data transitions without violating communication protocol requirements for direct current (DC) values. Although FIG. 1 shows the programmable circuitry 120 and termination resistors 122 as being separate from the high-speed transmitter 108 (between the transmitter 108 and the differential data line 130), alternative embodiments may combine these components together. Additional details for the programmable circuitry 120 are provided in FIG. 2.

FIG. 2 shows an embodiment of the programmable circuitry 120 described for FIG. 1. In the embodiment of FIG. 2, the programmable circuitry 120 comprises various circuitry portions designated herein as a first circuitry portion 250, a second circuitry portion 202, a third circuitry portion 207, a fourth circuitry portion 220, and a fifth circuitry portion 230. As will be described in greater detail, the first circuitry portion 250, the second circuitry portion 202, and the third circuitry portion 207 enable termination (ZHS) impedances 214A and 214B to be controlled. Firstly, the first, second and third circuitry portions allow ZHS impedances to be compensated for temperature drift and therefore maintain impedance matching with the external termination impedances ZTERM 280. Secondly, the first, second and third circuitry portions allow ZHS impedances to be programmed to compensate for external series impedances (ZSER) 260 added to the differential data line 130 between the circuitry 120 and the connector 270.

As a first example, the programmable circuitry 120 may be used to calibrate termination (ZHS) impedances 214A and 214B to match with the external termination impedances ZTERM 280 such that ZHS=ZTERM. As a second example, the programmable circuitry 120 may be used to program termination (ZHS) impedances 214A and 214B to compensate for an external series impedances (ZSER) 260 while maintaining matching with the external termination impedances ZTERM 280 at the connector 270 such that ZHS=ZTERM−ZSER.

As shown, the first circuitry portion 250 provides a current source IHSREF which should be first-order temperature independent. One implementation of such a current source is shown in FIG. 2. In this example, a bandgap reference voltage is applied to a resistive element 258 via a feedback loop comprising an amplifier 252 and a transistor 256. The resistive element 258 may take the form of, but is not limited to, an internal resistor, an external resistor, or a switched capacitor resistive element. The second circuitry portion 202 may comprise transistors 204 and 206. The transistor 204 controls a programmable current IREP based on IHSREF and a control signal (ZREP_PROG). The transistor 206 controls a fixed current IC1 based on IHSREF. In accordance with at least some embodiments, the transistors 204 represent a current digital-to-analog converter (DAC) (e.g., a 3-bit current DAC) with ZREP_PROG as the control signal. ZREP_PROG control signal is provided externally.

As shown, IREP is provided from the second circuitry portion 202 to the third circuitry portion 207. In accordance with at least some embodiments, the second circuitry portion comprises a finite state machine (FSM) 208 that provides a first control signal (RTERM—CAL) for a variable resistor (ZREP) and a second control signal (RTERM—RMX) for the variable ZHS impedances 214A and 214B. The operation of the FSM 208 is controlled in part by the output of a comparator 210 that compares an input signal (VREP) with a voltage reference (VHSREF).

In accordance with at least some embodiments, the ZHS impedances 214A, 214B represent a resistive digital-to-analog converter (DAC) or other programmable component with the input control code being provided by the FSM 208. To calibrate the ZHS impedances 214A and 214B, the third circuitry portion 207 is used. A replica (IREP) of the temperature independent output drive current (IHS) is applied through a replica (ZREP) of the temperature dependent ZHS impedances 214A, 214B. The calibration of ZREP generates a temperature dependent voltage (VREP) which is a proportional replica of the high level transmitter output voltage (VHSOH_conn).

VHSOH_ic is the transmitter output voltage of the transceiver 104 at the integrated circuit (IC) pins (pins DP and DM in FIG. 2). VHSOH_ic=IHS*(ZHS//((ZSER+ZTERM))=IHS*(ZHS*(ZSER+ZTERM)/(ZSER+ZHS+ZTERM)), where “//” denotes “in parallel with”. VHSOH_conn is the transmitter output voltage of the transceiver 104 measured at the connector 270. Hence VSHOH_conn=VHSOH_ic*(ZTERM/(ZSER+ZTERM))=IHS*ZHS*ZTERM/(ZSER+ZHS+ZTERM).

As shown ZHS=ZTERM−ZSER is required in order to compensate for an external series impedances (ZSER) 260 while maintaining matching with the external termination impedances ZTERM 280 at the connector 270. Substituting for this ZHS target in the VHSOH_conn equation results in VHSOH_conn=IHS*(ZTERM−ZSER)/2=IHS*ZHS/2.

VREP is compared to a temperature independent voltage reference (VHSREF) by the comparator 210 and the comparator\'s output is provided as a control signal to the FSM 208. The FSM 208 then outputs a control signal (e.g., a control code) to drive the termination ZHS impedances 214A and 214B up or down.

In FIG. 2, the second circuitry portion 202, the fourth circuitry portion 220, and the fifth circuitry portion 230 combined show that for a given IHS_PROG multiplication factor M (described later), IHS is related to IREP by a fixed current multiplication ratio Ki, where Ki is defined by the equation IREP=Ki*IHS. A fixed ratio between ZREP and ZHS is maintained irrespective of the calibrated value of ZREP, such that we can define ZREP=Kr*ZHS. If a resistive DAC is used for the ZHS impedances 214A and 214B, and for the replica (ZREP) impedance 212, the FSM 208 may sweep down a sequence of input codes for the replica resistive DAC ZREP 212 until the comparator 210 toggles from high to low. This sets the value of ZREP 212 and hence ZHS. In accordance with embodiments, the toggling occurs approximately when VHSREF=VREP. Since VREP=IREP*ZREP; and IREP=Ki*IHS; and ZREP=Kr*ZHS; and VHSOH_conn=IHS*(ZHS/2)); hence, VREP=2*Ki*Kr*VHSOH_conn. Since Ki and Kr are temperature independent factors and VHSREF is a bandgap voltage and is (to first-order approximation) temperature independent, VHSOH_conn can be made temperature independent. Thus, after calibration we have VREP=VHSREF=IREP*ZREP. Substituting for ZREP=Kr*ZHS and solving for ZHS, we have ZHS=(VHSREF/IREP)*(1/Kr). Therefore 3 independent variables are available with which to calibrate and program ZHS. By programming IREP, the ZHS impedances 214A and 214B can be made programmable.

In accordance with at least some embodiments, IREP is programmed using an offset current DAC (implemented by the second circuitry portion 202). For example, a DAC of 3-bits may be controlled by a digital signal ZREP_PROG allowing IREP to be independently adjusted by a multiplication factor P. In this case, the equation for ZHS becomes ZHS=(VHSREF/(IREP*P)*(1/Kr). Using this multiplication factor P, the ZHS impedances 214A, 214B can be reduced to compensate for series impedance on the differential data line 130. If VHSREF, Kr and the default value of IREP are set in order to calibrate for ZHS=ZTERM with multiplication factor P=1 (where P corresponds to a particular value of ZREP_PROG); then P can be programmed to compensate for external series impedances (ZSER) 260 by adjusting the calibration target to ZTERM−ZSER by setting P=ZTERM/(ZTERM−ZSER).

As an example, a system with termination impedances ZTERM 280 may have various external components (e.g., common mode filters), which may be coupled to the differential data line 130 and which present a combined series impedance ZSER 260. ZSER may be compensated by programming IREP in order to have ZHS=ZTERM−ZSER. A ZHS impedance reduction between 0 to N ohms (let N=3 in this example) may be sufficient to compensate for various external components (e.g., common mode filters). More specifically, if an external component adds approximately 0 ohms to the series impedance of the differential data line 130 which is terminated with termination impedances ZTERM 280 of 45 ohms, IREP is programmed so that each ZHS impedance 214A, 214B has a value of approximately 45 ohms. If an external component (or components) adds approximately 1 ohm to the series impedance of the differential data line 130, IREP is programmed so that each ZHS impedance 214A, 214B has a value of approximately 44 ohms. If an external component (or components) adds approximately 2 ohms to the series impedance of the differential data line 130, IREP is programmed so that each ZHS impedance 214A, 214B has a value of approximately 43 ohms. If an external component (or components) adds approximately 3 ohms to the series impedance of the differential data line 130, IREP is programmed so that each ZHS impedance 214A, 214B has a value of approximately 42 ohms.

When an external component (or components) is added to the differential data line 130, the high-level voltage at the transceiver 104 (VHSOH_ic) is not the same as the high-level voltage at connector 270 (VHSOH_conn) because VHSOH_conn is degraded by the serial impedance ZSER 260 on the differential data line 130. This may immediately be seen from the equation for VSHOH_conn described previously by setting ZHS=ZTERM−ZSER. The result is VHSOH_conn=IHS*(ZTERM−ZSER)/2, which is less than the target value of VHSOH=VHSOH_ic=VHSOH_conn=IHS*ZTERM/2 for matched line with ZSER=0 and ZHS=ZTERM. This degradation in VHSOH_conn may be compensated for by multiplying by an independent variable M such that VHSOH_conn=M*IHS*(ZTERM−ZSER)/2. For the case of no external series impedance present (i.e., ZSER=0), setting M=1 will make VHSOH_conn=IHS*ZTERM/2. For the case of an external series impedance ZSER present, setting M=(ZTERM/(ZTERM−ZSER)) will make VHSOH_conn=IHS*ZTERM/2.

In accordance with at least some embodiments, the fourth circuitry portion 220 is configured to adjust IHS by a multiplication factor M. As shown, the fourth circuitry portion 220 comprises transistors 222 and 224, which may represent an offset current DAC (e.g., a 4-bit DAC) or another programmable component controlled by a digital control signal IHS_PROG in order to set the IHS multiplication factor M. The IHS_PROG control signal may be provided externally. Increasing and decreasing IHS has a direct effect on the VHSOH_conn values. In other words, increasing IHS causes VHSOH_conn to increase. Alternatively, decreasing IHS causes VHSOH_conn to decrease. In accordance with at least some embodiments, the IHS values and the ZHS impedance values are controlled together. As previously discussed, the ZHS impedances 214A, 214B are programmable by controlling IREP (e.g., using the first circuitry portion 250, the second circuitry portion 202, and the third circuitry portion 207) and VHSOH is programmable by controlling IHS (e.g., using the fourth circuitry portion 220). As previously discussed, in some embodiments, IREP and IHS may be controlled using current DACs.

As an example Table 1A shows various parameter values and illustrates how VHSOH_conn values are affected by ZSER 260; Table 1B shows various parameter values and illustrates how VHSOH_conn values are affected by adjusting the ZHS impedances 214A, 214B to compensate for ZSER 260; and Table 1C shows various parameter values and illustrates how VHSOH_conn values are affected by adjusting the ZHS impedances 214A, 214B and a transmitter output current drive (IHS) multiplication factor M to compensate for ZSER 260. In Tables 1A-1C, it is assumed that the desired voltage level for VHSOH_conn is 400.0 mV with termination impedances ZTERM 280 of 45 ohms. For example, a particular communication protocol (e.g., USB 2.0) may specify that voltage levels for differential data communications be at 400 mV +/−10% (360 mV to 440 mV).

TABLE 1A ZSER (ohm) 0 1 2 3 IHS (mA) 17.78 17.78 17.78 17.78 M 1.000 1.000 1.000 1.000 ZHS (ohm) 45 45 45 45 ZTERM (ohm) 45 45 45 45 VHSOH_ic (mV) 400.0 404.4 408.7 412.9 VHSOH_conn (mV) 400.0 395.6 391.3 387.1

TABLE 1B ZSER (ohm) 0 1 2 3 IHS (mA) 17.78 17.78 17.78 17.78 M 1.000 1.000 1.000 1.000 ZHS (ohm) 45 44 43 42 ZTERM (ohm) 45 45 45 45 VHSOH_ic (mV) 400.0 400.0 400.0 400.0 VHSOH_conn (mV) 400.0 391.3 383.0 375.0

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