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Automatic control of clock duty cycle




Title: Automatic control of clock duty cycle.
Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops. ...

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USPTO Applicaton #: #20110109354
Inventors: Xiaoxin Feng, Weston Roper, James D. Seefeldt


The Patent Description & Claims data below is from USPTO Patent Application 20110109354, Automatic control of clock duty cycle.

This application is a divisional of U.S. application Ser. No. 12/455,572, filed Jun. 3, 2009, the entire content of which is incorporated herein by reference.

GOVERNMENT RIGHTS

The United States Government has acquired certain rights in this invention pursuant to Contract No. NNJ06TA25C, awarded by NASA Johnson Space Center.

TECHNICAL FIELD

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This disclosure relates to clock signal management, and more specifically, to duty cycle correction circuits for a clock signal.

BACKGROUND

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A phase-locked loop (PLL) is often utilized within clock generation and distribution systems of an integrated circuit. In general, a PLL generates an output signal having a phase that is matched to the phase of a reference signal. The PLL is typically implemented as a control loop with the output signal being used as a negative feedback signal to control the PLL. The PLL includes a phase detector that compares the reference clock signal to the feedback clock signal to determine whether the phases of the reference clock signal and the feedback clock signal are aligned.

In many PLLs, the phase detector will detect the rising edges of both signals to make this determination. Likewise, the control loop within the PLL generally moves only the rising edge of the output clock signal in order to achieve phase lock. At the same time, many existing duty cycle correction (DCC) circuits adjust both the rising and falling edges of a clock signal in order to achieve a desired duty cycle for the clock signal. Because the PLL and the DCC control loops both adjust the rising edge of the output clock signal, integrating a DCC within the control loop of a PLL can cause interference with the operation of the PLL.

SUMMARY

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In general, this disclosure is directed to a duty cycle correction (DCC) circuit configured to adjust a falling edge of a clock signal, and thereby adjust the duty cycle of the clock signal. The DCC may generate a pulse in response to a falling edge of an input clock signal. A feedback network compares the duty cycle of the output clock signal with a desired duty cycle and generates a control signal, which is used for delaying the pulse. An edge adjustment circuit adjusts the falling edge of the input clock signal based on the amount of delay in the delayed pulse. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC circuit may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

In one example, the disclosure is directed to a duty cycle correction circuit device that includes a pulse generator configured to generate a pulse in response to a falling edge of an input clock signal. The device further includes a voltage-controlled delay circuit configured to delay the pulse based on a control voltage. The device further includes an edge adjustment circuit configured to adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal. The device further includes a feedback circuit path configured to adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle.

In another example, the disclosure is directed to a method that includes generating a pulse in response to a falling edge of an input clock signal. The method further includes delaying the pulse based on a control voltage. The method further includes adjusting the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal. The method further includes adjusting the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle.

In another example, the disclosure is directed to a clock synthesizer system that includes a phase-locked loop forward circuit path configured to generate an intermediate clock signal based on a reference clock signal and a feedback clock signal. The system further includes a duty cycle correction circuit configured to adjust the falling edge of the intermediate clock signal to produce an output clock signal. The system further includes a feedback circuit path configured to apply the output clock signal to the phase-locked loop forward circuit path as the feedback clock signal.

In another example, the disclosure is directed to a method that includes generating an intermediate clock signal based on a reference clock signal and a feedback clock signal. The method further includes adjusting the falling edge of the intermediate clock signal to produce an output clock signal. The method further includes applying the output clock signal to the phase-locked loop forward circuit path as the feedback clock signal.

The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF DRAWINGS

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FIG. 1 is a block diagram illustrating an example clock synthesizer system according to this disclosure.

FIG. 2 is a block diagram illustrating an example duty cycle correction (DCC) circuit device according to this disclosure.

FIG. 3 is a block diagram illustrating another example DCC circuit device according to this disclosure.

FIG. 4 is a schematic diagram illustrating another example DCC circuit device according to this disclosure.

FIG. 5 is a timing diagram illustrating the timing of several signals within the example DCC of FIG. 4.

FIG. 6 is a schematic diagram illustrating a voltage-controlled delay element for use in any of the DCC circuits of this disclosure.

FIG. 7 is a flow diagram illustrating an example method for adjusting a duty cycle of a clock signal according to this disclosure.

FIG. 8 is a flow diagram illustrating an example method for generating a phase-aligned and duty cycle corrected clock signal.

FIG. 9 is a flow diagram illustrating an example method for generating a phase-aligned and duty cycle corrected clock signal.

DETAILED DESCRIPTION

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In general, this disclosure is directed to a duty cycle correction (DCC) circuit configured to adjust a falling edge of a clock signal. As used herein, a falling edge of a clock signal may refer to a transition within the clock signal from a high logic value to a low logic value. The DCC may generate a pulse in response to a falling edge of an input clock signal. A feedback network compares the duty cycle of the output clock signal with a desired duty cycle and generates a control signal, which is used for delaying the pulse. An edge adjustment circuit adjusts the falling edge of the input clock signal based on the amount of delay in the delayed pulse. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC circuit may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

FIG. 1 is a block diagram illustrating an example clock synthesizer system 10 according to this disclosure. Clock synthesizer system 10 generates an output clock signal that is phase-aligned with a reference clock signal and has a frequency that is a multiple of the frequency of the reference clock. Clock synthesizer system 10 includes a phase-locked loop (PLL) forward circuit path 12, a duty cycle correction (DCC) circuit 14, a frequency divider 16, a reference clock signal 18, an output clock signal 20, and signal nodes 22, 24.




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stats Patent Info
Application #
US 20110109354 A1
Publish Date
05/12/2011
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
/
Drawings
0


Duty Cycle Duty Cycle Correction

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20110512|20110109354|automatic control of clock duty cycle|In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay |Honeywell-International-Inc