FreshPatents.com Logo
stats FreshPatents Stats
2 views for this patent on FreshPatents.com
2011: 2 views
Updated: June 23 2014
newTOP 200 Companies filing patents this week


    Free Services  

  • MONITOR KEYWORDS
  • Enter keywords & we'll notify you when a new patent matches your request (weekly update).

  • ORGANIZER
  • Save & organize patents so you can view them later.

  • RSS rss
  • Create custom RSS feeds. Track keywords without receiving email.

  • ARCHIVE
  • View the last few months of your Keyword emails.

  • COMPANY DIRECTORY
  • Patents sorted by company.

Follow us on Twitter
twitter icon@FreshPatents

Automatic control of clock duty cycle

last patentdownload pdfimage previewnext patent


Title: Automatic control of clock duty cycle.
Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops. ...


USPTO Applicaton #: #20110109354 - Class: 327156 (USPTO) - 05/12/11 - Class 327 


view organizer monitor keywords


The Patent Description & Claims data below is from USPTO Patent Application 20110109354, Automatic control of clock duty cycle.

last patentpdficondownload pdfimage previewnext patent

This application is a divisional of U.S. application Ser. No. 12/455,572, filed Jun. 3, 2009, the entire content of which is incorporated herein by reference.

GOVERNMENT RIGHTS

The United States Government has acquired certain rights in this invention pursuant to Contract No. NNJ06TA25C, awarded by NASA Johnson Space Center.

TECHNICAL FIELD

This disclosure relates to clock signal management, and more specifically, to duty cycle correction circuits for a clock signal.

BACKGROUND

A phase-locked loop (PLL) is often utilized within clock generation and distribution systems of an integrated circuit. In general, a PLL generates an output signal having a phase that is matched to the phase of a reference signal. The PLL is typically implemented as a control loop with the output signal being used as a negative feedback signal to control the PLL. The PLL includes a phase detector that compares the reference clock signal to the feedback clock signal to determine whether the phases of the reference clock signal and the feedback clock signal are aligned.

In many PLLs, the phase detector will detect the rising edges of both signals to make this determination. Likewise, the control loop within the PLL generally moves only the rising edge of the output clock signal in order to achieve phase lock. At the same time, many existing duty cycle correction (DCC) circuits adjust both the rising and falling edges of a clock signal in order to achieve a desired duty cycle for the clock signal. Because the PLL and the DCC control loops both adjust the rising edge of the output clock signal, integrating a DCC within the control loop of a PLL can cause interference with the operation of the PLL.

SUMMARY

In general, this disclosure is directed to a duty cycle correction (DCC) circuit configured to adjust a falling edge of a clock signal, and thereby adjust the duty cycle of the clock signal. The DCC may generate a pulse in response to a falling edge of an input clock signal. A feedback network compares the duty cycle of the output clock signal with a desired duty cycle and generates a control signal, which is used for delaying the pulse. An edge adjustment circuit adjusts the falling edge of the input clock signal based on the amount of delay in the delayed pulse. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC circuit may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

In one example, the disclosure is directed to a duty cycle correction circuit device that includes a pulse generator configured to generate a pulse in response to a falling edge of an input clock signal. The device further includes a voltage-controlled delay circuit configured to delay the pulse based on a control voltage. The device further includes an edge adjustment circuit configured to adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal. The device further includes a feedback circuit path configured to adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle.

In another example, the disclosure is directed to a method that includes generating a pulse in response to a falling edge of an input clock signal. The method further includes delaying the pulse based on a control voltage. The method further includes adjusting the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal. The method further includes adjusting the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle.

In another example, the disclosure is directed to a clock synthesizer system that includes a phase-locked loop forward circuit path configured to generate an intermediate clock signal based on a reference clock signal and a feedback clock signal. The system further includes a duty cycle correction circuit configured to adjust the falling edge of the intermediate clock signal to produce an output clock signal. The system further includes a feedback circuit path configured to apply the output clock signal to the phase-locked loop forward circuit path as the feedback clock signal.

In another example, the disclosure is directed to a method that includes generating an intermediate clock signal based on a reference clock signal and a feedback clock signal. The method further includes adjusting the falling edge of the intermediate clock signal to produce an output clock signal. The method further includes applying the output clock signal to the phase-locked loop forward circuit path as the feedback clock signal.

The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating an example clock synthesizer system according to this disclosure.

FIG. 2 is a block diagram illustrating an example duty cycle correction (DCC) circuit device according to this disclosure.

FIG. 3 is a block diagram illustrating another example DCC circuit device according to this disclosure.

FIG. 4 is a schematic diagram illustrating another example DCC circuit device according to this disclosure.

FIG. 5 is a timing diagram illustrating the timing of several signals within the example DCC of FIG. 4.

FIG. 6 is a schematic diagram illustrating a voltage-controlled delay element for use in any of the DCC circuits of this disclosure.

FIG. 7 is a flow diagram illustrating an example method for adjusting a duty cycle of a clock signal according to this disclosure.

FIG. 8 is a flow diagram illustrating an example method for generating a phase-aligned and duty cycle corrected clock signal.

FIG. 9 is a flow diagram illustrating an example method for generating a phase-aligned and duty cycle corrected clock signal.

DETAILED DESCRIPTION

In general, this disclosure is directed to a duty cycle correction (DCC) circuit configured to adjust a falling edge of a clock signal. As used herein, a falling edge of a clock signal may refer to a transition within the clock signal from a high logic value to a low logic value. The DCC may generate a pulse in response to a falling edge of an input clock signal. A feedback network compares the duty cycle of the output clock signal with a desired duty cycle and generates a control signal, which is used for delaying the pulse. An edge adjustment circuit adjusts the falling edge of the input clock signal based on the amount of delay in the delayed pulse. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC circuit may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

FIG. 1 is a block diagram illustrating an example clock synthesizer system 10 according to this disclosure. Clock synthesizer system 10 generates an output clock signal that is phase-aligned with a reference clock signal and has a frequency that is a multiple of the frequency of the reference clock. Clock synthesizer system 10 includes a phase-locked loop (PLL) forward circuit path 12, a duty cycle correction (DCC) circuit 14, a frequency divider 16, a reference clock signal 18, an output clock signal 20, and signal nodes 22, 24.

PLL forward circuit path 12 is configured to generate a phase-adjusted signal 24 that is phase-aligned with a reference clock signal 18. PLL forward circuit path 12 receives feedback signal 22, which is used to control the phase and/or frequency of phase-adjusted signal 24. In general, PLL forward circuit path 12 determines a phase difference between reference clock signal 18 and feedback clock signal 22, and adjusts the frequency of phase-adjusted signal 24 such that the resulting phase and frequency of feedback signal 22 matches, or has a fixed relation to, the phase and frequency of reference clock signal 18. In one example, PLL forward circuit path 12 determines the phase difference by measuring a time difference between the rising edges of reference clock signal 18 and feedback clock signal 22.

PLL forward circuit path 12 may include any components that are generally found in the forward circuit path of an analog or digital PLL control loop. As used herein, forward circuit path refers to all of or a portion of a PLL control loop that is not part of the feedback path of such control loop. In one example, PLL forward circuit path 12 may include a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector compares the phase and/or frequency of feedback signal 22 relative to reference clock signal 18 and generates an error signal based on the phase difference between these signals. The loop filter filters the error signal to remove higher order frequency components from the error signal and to produce a filtered error signal. The VCO generates an output clock signal having a frequency that is determined by the filtered error signal.

PLL forward circuit path 12 is described above is merely an exemplary PLL forward circuit path. It should understood that any forward circuit path that is capable of implementing PLL functionality may be used for PLL forward circuit path 12 in clock synthesizer system 10 of FIG. 1. PLL forward circuit path 12 may include different components than described above and/or components arranged in the same or different order without departing from the scope of this disclosure. For example, PLL forward circuit path 12 may include a digital phase detector, a counter, and a digitally-controlled oscillator. As another example, PLL forward circuit path 12 may be implemented without a loop filter. In any case, PLL forward circuit path 12 includes components that provide the functionality for all of or a portion of a PLL control loop excluding the feedback contained with the control loop.

DCC circuit 14 is configured to adjust the duty cycle of phase-adjusted signal 24 in order to generate output clock signal 20. The steady-state output of DCC circuit 14 has a duty cycle that is substantially matched to a desired duty cycle. According to this disclosure, DCC circuit 14 adjusts the timing of the falling edge of phase-adjusted signal 24 in order to achieve the desired duty cycle. Since DCC circuit 14 adjusts the falling edge of the output clock signal to achieve a desired duty cycle, DCC circuit 14 may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

In one example, DCC circuit 14 generates a pulse in response to a falling edge of an input clock signal, delays the pulse based on a control voltage, adjusts the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjusts the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. In this manner, DCC circuit 14 provides a control loop that controls the falling edge of output clock signal 20 in order to achieve a desired duty cycle.

In some examples, DCC circuit 14 may contain a sequential circuit element with an asynchronous reset input that forces output clock signal 20 to a low logic value when a pulse is received at the input. In some cases, the sequential circuit element may also force output clock signal 20 to a high logic value when a rising edge is received from incoming, phase-adjusted clock signal 24. Thus, the sequential circuit element of DCC circuit 14 may adjust the duty cycle of incoming clock signal 24 without disturbing and/or adjusting the rising edge of output clock signal 20.

In additional examples, DCC circuit 14 may include an analog feedback loop that does not require the use of a pre-existing external clock or oscillator to control the feedback loop. In such examples, the analog feedback loop may utilize a reference voltage input that can be used to adjust the desired duty cycle after construction of the circuit. By using a reference voltage within an analog feedback loop, as opposed to a digital feedback loop or state machines, the desired duty cycle can be more precisely programmed and/or adjusted in some examples.

In further examples, DCC circuit 14 may include a voltage-controlled delay unit that utilizes current-starved inverters for adjustment of the pulse delay. In such examples, the control voltage may, in some cases, adjust the current flowing into the current-starved inverters from both the high voltage power supply and from the low voltage power supply.

In additional examples, DCC circuit 14 captures the falling edge of incoming clock signal 24 in order to generate a pulse used for controlling the falling edge of output clock signal 20. By generating a pulse based on the falling edge of the incoming clock signal, rather than the rising edge, a more compact delay circuit can be implemented because the operating range of the delay parameter is effectively reduced. In addition, when the pulse is based on the falling edge of the incoming clock signal, the overall amount of delay required for the pulse can be reduced, allowing for more stable operation of the clock synthesizer control loop.

Frequency divider 16 is configured to generate a frequency-divided output clock signal 22 based on output clock signal 20. Frequency divider 16 reduces the frequency by a pre-set or programmed factor. The frequency-divided output clock signal may be applied to PLL forward circuit path 12 along a feedback path. Frequency divider 16 may be configured to receive a programmable integer, N, which is used as the divisor for the frequency division. In one example, frequency divider 16 may be implemented as a modulo-N counter. The modulo-N counter may increase its count by a value of one for each period of output clock cycle 20. The modulo-N counter produces feedback clock signal 22 such that the period of feedback clock signal 22 is defined according to the time required for modulo-N counter to cycle through all N states. In this manner, frequency divider 16 divides the frequency of output clock signal 20 to produce feedback clock signal 22. Although described above with respect to a digital counter, it should be recognized that frequency divider 16 can be implemented using other analog and/or digital techniques known in the art.

During operation of clock synthesizer system 10, PLL forward circuit path 12 receives reference clock signal 18 and feedback clock signal 22. PLL forward circuit path 12 generates phase-adjusted signal 24 based on a phase difference between reference clock signal 18 and feedback signal 20. PLL forward circuit path 12 uses the rising edges of signals 18, 20 to determine the phase difference. Based on this phase difference, PLL forward circuit path 12 adjusts the rising edge of phase-adjusted signal 24 to achieve a fixed amount of phase delay (i.e., phase lock). Phase-adjusted signal 24 is fed into DCC circuit 14.

DCC circuit 14 adjusts the duty cycle of phase-adjusted signal 24 such that the duty cycle of output clock signal 20 is substantially equal to a desired duty cycle. In particular, DCC circuit 14 adjust the duty cycle by adjusting the falling edge of the phase-adjusted clock signal 24 without varying the rising edge of phase-adjusted clock signal 24. Frequency divider 16 reduces the frequency of output signal 20 by a programmable factor, N. Frequency-divided clock signal 16 is applied to PLL forward circuit path 12 as feedback signal 22. Since PLL forward circuit path 12 attempts to match both the frequency and phase of reference clock signal 18 and feedback clock signal 20, PLL forward circuit path 12 adjusts phase-adjusted signal 24 such that the frequency of phase-adjusted signal 24 is N times the frequency of reference clock signal 18. In this manner, clock synthesizer system 10 provides a phase-locked and duty-cycle corrected output signal having a frequency that is a multiple of the reference clock signal frequency.

Although the example clock synthesizer system 10 in FIG. 1 is depicted as including a frequency divider, it should be understood that other example clock synthesizers that utilize the techniques of this disclosure may not utilize a frequency divider. In such cases, the techniques in this disclosure may provide a combined PLL-DCC control loop without stepping up the frequency.

FIG. 2 is a block diagram illustrating an example duty cycle correction (DCC) circuit 40 device according to this disclosure. DCC circuit 40 is configured to adjust the falling edge of an input clock signal to produce an output clock signal having a duty cycle substantially equal to a desired duty cycle. In some examples, DCC circuit 40 of FIG. 2 may be used to form DCC circuit 14 of FIG. 1. DCC circuit 40 includes a pulse generator 42, a voltage-controlled delay unit 44, an edge adjustment circuit 46, a feedback path 48, an input clock signal 50, an output clock signal 52, and signal nodes 54, 56, 58.

Pulse generator 42 is configured to generate a pulse in response to a falling edge of an input clock signal. Pulse generator 42 may be implemented with combinatorial logic, sequential logic and/or analog circuits as is known in art. In some examples, DCC circuit 40 captures the falling edge of an incoming clock signal in order to generate a pulse signal 54 used for controlling the falling edge of output clock signal 20. By generating a pulse based on the falling edge of the incoming clock signal, rather than the rising edge, a more compact delay circuit can be implemented because the operating range of the delay parameter is effectively reduced.

Voltage-controlled delay unit 44 is configured to receive pulse signal 54 generated by pulse generator 42, and to delay pulse signal 54 based on a control voltage 56. In some examples, voltage-controlled delay unit 44 may includes a voltage-to-current converter followed by one or more current-starved inverters. In some cases, the supply current for both the high voltage supply and the low voltage supply may be adjusted based on the control voltage.

In any case, voltage-controlled delay unit 44 generates a delayed pulse signal 58 corresponding to pulse signal 54. The amount of delay is controlled by control voltage 56. Because pulse signal 54 is based on the falling edge of input clock signal 50, as opposed to the rising edge, the overall amount of delay required to achieve a desired duty cycle can be reduced thereby allowing for more stable operation of the clock synthesizer control loop.

Edge adjustment circuit 46 is configured to adjust the falling edge of input clock signal 50 based on delayed pulse signal 58 in order to produce an output clock signal 52. In some examples, edge adjustment circuit 46 may include one or more sequential circuit elements. The sequential circuit element may be configured to force output clock signal 52 to a low logic value when a pulse is detected within pulse signal 58. In some examples, the sequential circuit element may also force output signal 52 to a high logic value when a rising edge is detected within incoming clock signal 50. Thus, the sequential circuit element may adjust the duty cycle of incoming clock signal 24 without disturbing and/or adjusting the rising edge of output clock signal 20. In other examples, edge adjustment circuit 46 may be implemented with other types of combinatorial and/or analog circuitry.

Feedback path 48 is configured to adjust control voltage signal 56 based on the difference between a duty cycle of output clock signal 52 and a desired duty cycle. The desired duty cycle may be hard-wired or programmed into feedback path 48. In some examples, a reference voltage input controls the desired duty cycle.

In some examples, feedback path 48 may include circuitry that measures the duty cycle of output clock signal 52 by generating a first voltage substantially proportional to the duty cycle of the output clock. Feedback path 48 may compare the first voltage to a reference voltage representative of a desired duty cycle, and output a control voltage substantially proportional to a difference between the measured duty cycle and the reference voltage. In additional examples, feedback path 48 may be implemented as an analog feedback path, which does not require the use of a pre-existing external clock or oscillator to control the feedback loop.



Download full PDF for full patent description/claims.

Advertise on FreshPatents.com - Rates & Info


You can also Monitor Keywords and Search for tracking patents relating to this Automatic control of clock duty cycle patent application.
###
monitor keywords



Keyword Monitor How KEYWORD MONITOR works... a FREE service from FreshPatents
1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored.
3. Each week you receive an email with patent applications related to your keywords.  
Start now! - Receive info on patent apps like Automatic control of clock duty cycle or other areas of interest.
###


Previous Patent Application:
Summation circuit in dc-dc converter
Next Patent Application:
Digital pll circuit and method of controlling the same
Industry Class:
Miscellaneous active electrical nonlinear devices, circuits, and systems
Thank you for viewing the Automatic control of clock duty cycle patent info.
- - - Apple patents, Boeing patents, Google patents, IBM patents, Jabil patents, Coca Cola patents, Motorola patents

Results in 0.79793 seconds


Other interesting Freshpatents.com categories:
Medical: Surgery Surgery(2) Surgery(3) Drug Drug(2) Prosthesis Dentistry  

###

All patent applications have been filed with the United States Patent Office (USPTO) and are published as made available for research, educational and public information purposes. FreshPatents is not affiliated with the USPTO, assignee companies, inventors, law firms or other assignees. Patent applications, documents and images may contain trademarks of the respective companies/authors. FreshPatents is not affiliated with the authors/assignees, and is not responsible for the accuracy, validity or otherwise contents of these public document patent application filings. When possible a complete PDF is provided, however, in some cases the presented document/images is an abstract or sampling of the full patent application. FreshPatents.com Terms/Support
-g2--0.6827
     SHARE
  
           

FreshNews promo


stats Patent Info
Application #
US 20110109354 A1
Publish Date
05/12/2011
Document #
12902773
File Date
10/12/2010
USPTO Class
327156
Other USPTO Classes
International Class
03L7/06
Drawings
10


Duty Cycle
Duty Cycle Correction


Follow us on Twitter
twitter icon@FreshPatents