Phase-locked-loop circuit   

The invention relates generally to phase-locked loop (PLL) circuits for generating synchronized phase and frequency signals from multi-phase reference signals.

A phase locked loop (PLL) circuit is a closed loop circuit that generates a synchronized output signal from a reference signal. The PLL circuit automatically responds to the frequency and phase of the reference signal by adjusting the output signal until the output signal is matched to the reference signal in both frequency and phase. In a power control system, for example, the PLL circuit detects the phase information of the grid voltage, so that a power controller can synchronize a converter\'s output voltage with the grid voltage. During a transient event such as a short circuit fault in power system, the phase angle and magnitude of the reference signal may change significantly, and it is desirable for the PLL circuit to provide a quick response.

In accordance with an embodiment disclosed herein, a phase-locked loop circuit comprises a phase error detector for receiving a multi-phase reference signal and a synchronized phase signal of the phase-locked-loop circuit, and for performing a rotational transformation to convert the multi-phase reference signal into two-phase quantities at a synchronous rotation d-q reference frame. A monotonic transfer module receives the two-phase quantities, and generates a monotonic phase error signal which is monotonic when a phase difference between the multi-phase reference signal and the synchronized phase signal ranges from −180 degrees to 180 degrees. A regulator receives the monotonic phase error signal, and generates a synchronized rotation frequency. An integrator receives the synchronized rotation frequency, and generates the synchronized phase signal.

These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

FIG. 1 is a block diagram of a conventional phase-locked-loop (PLL) circuit.

FIG. 2 illustrates a rotational transformation of a phase detector of the PLL circuit of FIG. 1, wherein a phase error is less than 90 degrees.

FIG. 3 illustrates a rotational transformation of the phase detector of the PLL circuit of FIG. 1, wherein a phase error is greater than 90 degrees.

FIG. 4 illustrates a sine-wave characteristic of the phase error detector of the PLL circuit of FIG. 1.

FIG. 5 is a block diagram of an exemplary PLL circuit according to one embodiment of the invention.

FIGS. 6 and 7 illustrate monotonic characteristics of a monotonic transfer module according different embodiments of the invention.

FIGS. 8-10 are block diagrams of monotonic transfer modules according to other embodiments of the invention.

DETAILED DESCRIPTION

Embodiments of the invention relate to a phase-locked-loop (PLL) circuit for generating synchronized phase and frequency signals from a multi-phase reference signal. The PLL circuit comprises a phase detector for receiving the multi-phase reference signal and a feedback synchronized phase signal and generating two-phase signals in a two-phase direct and quadrature (d-q) reference frame. The PLL circuit comprises a monotonic transfer function for receiving the two-phase signals in the d-q reference frame and for generating a phase error signal. The phase error signal is monotonic for a phase difference between the reference signal and the synchronized phase signal over the range from −180 degrees to 180 degrees.

To better understand the invention, reference is first made to a conventional PLL circuit 10 through FIGS. 1-4. As illustrated in FIG. 1, the illustrated PLL circuit 10 comprises a phase detector 12 for receiving a multi-phase reference signal 14 and a synchronized output signal 16 of PLL circuit 10 and for using these signals to generate a phase error signal 18. A regulator 20 determines a synchronized frequency (ωe) based on the phase error signal 18. An integrator 22 generates a synchronized phase signal (δ), and thus an output signal of the PLL circuit may include synchronized frequency (ωe) and phase (δ) signals.

When reference signal 14 is a balanced three-phase sinusoidal reference signal with voltage phasors (Va, Vb, and Vc), it can be expressed as equation 1 below:

[ V a V b V c ] = V m  [ sin   ω   t sin  ( ω   t - 2  π / 3 ) sin  ( ω   t + 2  π / 3 ) ] , equation   1

wherein “Vm” is a voltage amplitude of positive sequence, and “ω” is a fundamental rotational frequency of the three-phase reference signal 14.

Referring to FIG. 2, generation of phase error signal 18 by phase detector 12 typically comprises a rotational transformation. Phase detector 12 may transform the three-phase reference signal (Va, Vb, and Vc) into two-phase quantities (Vα, Vβ) in a two-phase stationary α-β reference frame according to equation 2 below for example:

[ V α V β ] = 2 3 × [ 1 - 0.5` - 0.5 0

Download full PDF for full patent description/claims.




You can also Monitor Keywords and Search for tracking patents relating to this Phase-locked-loop circuit patent application.

Patent Applications in related categories:

20130120037 - Agile clocking with receiver pll management - A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change ...

20130120036 - Apparatus and method for recovering burst-mode pulse width modulation (pwm) and non-return-to-zero (nrz) data - A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, ...

20130120035 - Lock detector and method of detecting lock status for phase lock loop - A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. ...

20130120038 - Phase-locked-loop with quadrature tracking filter for synchronizing an electric grid - Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. A phase-locked-loop (PLL) operation may be performed on the quadrature signal to monitor a voltage vector between the grid and ...

20130120039 - Phase-locked-loop with quadrature tracking filter for synchronizing an electric grid - Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. The inputs to the QTF may be either single input, multiple outputs, or alternatively, multiple inputs, multiple outputs. Furthermore, the ...


###


Other recent patent applications listed under the agent General Electric Company:

20090314099 - Apparatus and system for cyclic testing
20090314100 - System and method for cyclic testing
20090305079 - Brazed articles, braze assemblies and methods therefor utilizing gold/copper/nickel brazing alloys
20090305932 - Composition for removing engine deposits from turbine components
20090293994 - High thermal gradient casting with tight packing of directionally solidified casting
20090294566 - Methods for spiral winding composite fan bypass ducts and other like components
20090294567 - Spiral winding systems for manufacturing composite fan bypass ducts and other like components
20090297335 - Asymmetric flow extraction system