Methods and apparatus to manage ground fault conditions with a single coil   

This application is a divisional of U.S. Nonprovisional patent application Ser. No. 11/923,365, filed Oct. 24, 2007, which claims the benefit of U.S. Provisional Application Ser. No. 60/864,068 filed Nov. 2, 2006, U.S. Provisional Application Ser. No. 60/864,056 filed Nov. 2, 2006, and U.S. Provisional Application Ser. No. 60/864,058 filed Nov. 2, 2006, all of which are hereby incorporated by reference in their entireties.

This disclosure relates generally to ground fault interruption and, more particularly, to methods and apparatus to manage ground fault conditions with a single coil.

Electrical power distribution typically includes multiple-conductor wires to transmit electrical energy and facilitate a ground path for safety. A shock hazard exists in the event of an unintended path from the conductor wires or surfaces (such as a chassis of electrical equipment), which carry electric current, and the ground path. The conductors, such as a line conductor (also referred to as “hot”) and a neutral, or common, conductor, may leak electrical current to each other, to ground, and/or to a person or object as an intermediate path to ground. As such, a person in the intermediate path may receive a lethal electrical shock.

Ground fault circuit interrupters (GFCIs) may minimize and/or eliminate the risk of electrical shock by monitoring an imbalance of electrical current between the hot and neutral lines. Generally speaking, a line-to-ground fault may be detected by way of a coil (e.g., a toroidal Hall-effect coil) around the line and neutral conductors that provide electrical energy to a load. Under non-fault operating conditions, the magnetic fields that result from current in the hot conductor cancel with the magnetic fields that result from an opposite current flow in the neutral conductor, thereby failing to induce a corresponding electrical current in the coil. However, if current from the line conductor leaks current to ground, then the neutral conductor current, and its corresponding magnetic field, will be less than the magnetic field of the line conductor, thereby affecting the coil to produce a corresponding electrical signal indicating a fault. The electrical coil signal, such as a current value, may be compared to a threshold which, when exceeded, causes the GFCI to force a mechanical break to the load via, for example, a circuit interrupter. The circuit interrupter may be employed as a double pole, single throw switch that, when activated, physically separates the line and the neutral conductors from the load.

Detecting a neutral-to-ground fault poses additional challenges because, in part, the neutral conductor is also grounded at the source. Such double grounding of the neutral conductor could create a situation where a portion of the fault current from the line conductor returns to the source through the neutral conductor. As a consequence, the traditional single coil approach will not detect a flux imbalance representative of the actual current leakage magnitude. To aid in neutral-to-ground fault detection, a second coil is typically employed that, when coupled to the first coil, produces a positive feedback loop. Despite the lower detected current imbalances observed during a neutral-to-ground fault, which may not exceed a tripping threshold, the coupled coils will develop an oscillation that, when detected, may be used to indicate a circuit trip or interruption is warranted. Additionally or alternatively, a signal may be injected on the second coil so that, in the event of a neutral to ground fault, the injected signal is induced in the neutral line and is detected by the first coil.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a prior art ground fault circuit interrupter.

FIG. 2 is a block diagram of an example ground fault detector in which ground faults may be detected with a virtual inductor and a single sense coil.

FIGS. 3A and 3B are an equivalent circuit diagram and a corresponding output plot for the example ground fault detector device of FIG. 2 during non-fault conditions.

FIGS. 4A and 4B are an equivalent circuit diagram and a corresponding output plot for the example ground fault detector device of FIG. 2 during a neutral-to-ground fault.

FIGS. 5A and 5B are an equivalent circuit diagram and a corresponding output plot for the example ground fault detector device of FIG. 2 during a line-to-ground fault.

FIG. 6 is an example output plot for the example ground fault detector device of FIG. 2 during both a neutral-to-ground fault and a line-to-ground fault.

FIG. 7 is a flowchart representative of an example process to implement fault detection in the example ground fault detector device of FIG. 2.

FIG. 8A is a block diagram of another example ground fault detector in which ground faults may be detected with a single sense coil.

FIGS. 8B-8D are example equivalent circuits for the example ground fault detector of FIG. 8A during a non-fault condition, a neutral-to-ground fault, and a line-to-ground fault, respectively.

FIG. 9 is a block diagram of an example ground fault detector to detect fault conditions and simulate a saturation capacitor.

FIG. 10 is a block diagram of an example ground fault detector to perform an automatic self-test.

FIG. 11 includes example output plots for the example ground fault detector of FIG. 10 during self-test conditions.

FIG. 12 is a flowchart representative of an example process to implement a self-test of the example ground fault detector device of FIG. 10.

FIG. 13 is a block diagram of an example ground fault detector to perform a substantially continuous self-test.

FIGS. 14A and 14B are block diagrams of example fault separation circuits to facilitate substantially continuous self-test in the example ground fault detector device of FIG. 13.

FIG. 15 is a flowchart representative of an example process to implement substantially continuous self-testing of the example ground fault detector device of FIG. 13.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a prior art ground fault circuit interrupter (GFCI) 100. The GFCI 100 electrically connects to a line (or “hot”) conductor 102, a neutral conductor 104, and in some instances, a ground conductor 106. During normal operating conditions, the GFCI 100 provides electrical power via the line conductor 102 and neutral conductor 104 to an electrical load 108. However, a solenoid relay contact 110 may break electrical contact with the load 108 if a fault should occur. For example, faults having a resistive value may occur between the line conductor 102 to ground 106 (RLG) or from the neutral conductor 104 to ground 106 (RNG).

As shown in FIG. 1, a first sense coil 112 monitors for a current imbalance between the line conductor 102 and the neutral conductor 104 that may occur when a fault condition between these two conductors is present. For example, if no fault condition is present, then all such current carried by the line conductor 102 is also carried by the neutral conductor 104, but in the opposite direction. When a fault occurs, some of the current provided by the line conductor 102 takes an alternate path that bypasses the first sense coil 112, thereby causing n current (I1) induced to a secondary winding 114 of the first sense coil 112. Generally speaking, the sense coil may be employed as a toroidal coil constructed with high permeability laminated steel rings. A primary of the sense coil may be a single turn, through which the line and neutral conductors pass, while a secondary winding of the sense coil may include, for example, approximately 200 to 1500 turns. Current values detected by the first coil 112 are received by a ground fault detector circuit 116 powered by a bridge circuit 117, and such received signals are compared against a threshold, which is typically established in view of regulatory standards (e.g., Underwriters Laboratories). The established threshold(s) may pertain to a maximum current threshold (e.g., trip if the detected current exceeds a root mean square value of 6 milliamps) and/or a maximum duration of observed current imbalance (e.g., trip if detected current is sustained for more than three line-cycles). The ground fault detector circuit 116 responds to an exceeded threshold by sending one or more signals to a switching device 118, such as a silicon controlled rectifier (SCR), which may drive the solenoid relay contacts 110 to break the electrical contact with the load 108.

In the event of a neutral to ground fault, the first sense coil 112 may not sense any current imbalance, thus fail to trip the solenoid relay contact(s) 110. To detect a neutral to ground fault (RNG), a second coil 120 is employed having a secondary coil winding 122 to which the ground fault detector circuit 116 applies an oscillation signal. During non-fault operating conditions, the signal is not induced into the conductors because there is no impedance imbalance between the line conductor 102 and the neutral conductor 104 (no path between neutral and ground). However, in the event of a ground to neutral fault, the applied oscillation signal from the second coil 120 will propagate to the neutral-to-ground path and is then sensed by the first sense coil 112. When the corresponding oscillation signal is detected by the first sense coil 112, and processed by the ground fault detector circuit 116, the switching device may cause the relay contact 110 to break electrical contact.

The GFCI 100 also includes a test switch 124 and fault resistor RF to allow an end user (e.g., a homeowner) to verify that the GFCI 100 is working properly. When the test switch 124 is activated, current from the line conductor 102 passes through the first sense coil 112 in a first direction, but is diverted through RF and the test switch 124 to the neutral conductor 104. As a result, the returning current (in a second/opposite direction) on the neutral conductor 104 as it passes through the first sense coil 112 is less than the current on the line conductor 102 when it passes through the first sense coil 112, which causes a detected current imbalance between the line conductor 102 and the neutral conductor 104. However, a manual test process with the test switch 124 may not be a regular practice of the end user, which may mean that the end user is not protected in the event of a fault that may have occurred in between manual tests, if any.

The GFCI 100 also includes a saturation capacitor (CS) for the first sense coil 112 and the second coil 120 to, in part, prevent and/or minimize saturation of one or more voltage-to-current amplifiers that are connected to the coils. For example, an amplifier and/or a voltage-to-current amplifier/converter typically has a very low input impedance when configured with negative feedback. The secondary sense coil winding 114 behaves as an inductor and operates similar to a short circuit at low frequencies. Such operation creates a very high gain configuration, thus small direct current (DC) offsets that are typically present in operational amplifiers (OPAMPS) and/or similar devices may saturate the output. The output saturation may be eliminated with CS, which operates as a DC block yet allows AC signals to pass therethrough. Capacitors must typically have relatively large values to both block DC and pass household line frequency signals (e.g., 50 Hz, 60 Hz), which correspond to added manufacturing costs for the GFCI 100. Additionally, added cost results from having multiple coils within the GFCI 100.

The various methods and apparatus described herein may facilitate ground fault detection without a second coil, thereby eliminating an additional potential point of failure and enabling a cost savings opportunity that may be passed on to end users. Furthermore, the methods and apparatus described herein may facilitate sense coil operation with a smaller capacitor, thereby saving additional costs related to manufacture of the ground fault detection device. While self test techniques may still be performed by the end user, the apparatus and methods described herein may facilitate automatic self testing on a periodic and/or continuous basis to allow identification of unsafe conditions before an end user is exposed to potential danger due to, for example, failure of one or more parts of a ground fault detection device to operate correctly. Some or all of the methods and apparatus described above may be used with one another.

Turning to FIG. 2, a portion of a ground fault detector device 200 is shown having a ground fault detector circuit 202. The example ground fault detector circuit 202 (GFDC) may operate instead of, for example, the ground fault detector circuit 116 and corresponding second coil 120 of FIG. 1. The ground fault detector circuit 202 receives signals from a sense coil 204 having a primary winding through which a line conductor 206 and a neutral conductor 208 pass. As described in further detail below, the sense coil 204 allows the GFDC 202 to detect a current imbalance between the line conductor 206 and the neutral conductor 208 during fault conditions. Moreover, the GFDC 202 may detect a fault between the line conductor 206 and a ground 210, and/or the neutral conductor 208 and the ground 210.

The sense coil 204 includes a secondary winding (L1), which is connected in parallel with a capacitor (C1) and an active inductor (L2) that is simulated by voltage to current converters GM2, GM3, and a capacitor C2. Persons having ordinary skill in the art will appreciate that the voltage to current converters GM2, GM3, and the capacitor C2 may be referred to as a virtual inductor 214. The value of L2 is designed to be much smaller than L1, thus the overall inductance value of the parallel combination of L2 and L1 has a value of, for all practical purposes, L2. The parallel combination of the inductors (L1 and L2) and C1 form a resonance circuit, such as an LC tank that is also in parallel with a negative resistance (formed by transconductance GM1 in positive feedback) 212, which operates as a driving source to generate oscillations. The amplitude of oscillations may be limited with a limiter 215, as shown in FIG. 2. The limiter 215 may include, but is not limited to, a pair of diodes, zener diodes, etc. In the illustrated GFDC of FIG. 2, the virtual inductor L2 214 may perform a dual role that a traditional inductor may not facilitate. In particular, the virtual inductor L2 214 allows oscillations by virtue of the LC tank and, unlike a traditional inductor, also allows the measurement of the current going through. Since L2 is much smaller than L1, almost the totality of the current induced into the secondary winding 114 caused by a neutral to ground fault, can be measured.

A saturation capacitor CS is shown in series with L1 to minimize and/or eliminate amplifier saturation during DC conditions. However, CS may be reduced as a cost savings initiative while preserving saturation prevention, as described in further detail below. Persons having ordinary skill in the art will appreciate that voltage-to-current converters may be rated by a transconductance value gM. The transconductance is a ratio of the output current and an input voltage. Additionally, negative resistors may be implemented by, for example, one or more voltage-to-current amplifiers. A low pass filter 216 and neutral-to-ground (NG) detector 218 are connected to the output of the virtual inductor 214, and a switch driver 220 is connected to the NG detector 218 and a line-to-ground (LG) detector 222, discussed in further detail below. The example switch driver 220 may include a gate driver control for solid state switching devices such as, for example, bi-polar junction transistors (BJTs), metal oxide field effect transistors (MOSFETs), silicon controlled rectifiers (SCRs), etc.

If no fault condition is present (i.e., an NG and/or an LG fault), then L1, C1, −R1 (or GM1), and the virtual inductor 216 operate as a non-fault equivalent circuit 302 shown in FIG. 3A. In the illustrated non-fault equivalent circuit 302 of FIG. 3A, the voltage at node V1 is proportional to the current IL passing through the virtual inductor L2. Voltage V1 may be represented as shown below in Equation 1.

V 1 = I L G M   3 ( Equation   1 )

The equivalent circuit of FIG. 3A behaves as an oscillator to produce an oscillating current IL, having a resonance frequency (f) as represented by Equation 2. The resonance frequency may be detected by the NG detector 218.

f = 1 2  π   L 2  C ( Equation   2 )

The NG detector 218 may be implemented in one or more ways including, but not limited to, a full wave rectifier connected to a comparator, a digital filter, etc. However, the resonance frequency component at node V1 is blocked by the low pass filter 216 so that, under non-fault conditions, node V1 includes a resonance frequency component while node V2 does not include the resonance frequency component, as shown in FIG. 3B. The LG detector 222 may be employed to confirm that no faults exist by, for example, verifying the magnitude of signal at node V2 is small enough.

If a neutral-to-ground (NG) fault is present, then the example GFDC 202 may be electrically represented by a neutral-to-ground (NG) equivalent circuit 402 shown in FIG. 4A. In the illustrated NG equivalent circuit 402 of FIG. 4A, resistor R2 represents the NG resistance, which disrupts the oscillation previously established by the combination of L1, C1, −R1, and L2. The value of R2 is shown below in Equation 3.

R2=n2*RG  (Equation 3)

In the example Equation 3, n is the number of turns of the coil L1, and RG is the NG resistance. When R2 is less than the negative resistance R1, the overall resistive value becomes positive and there is no longer a condition for oscillation and the resonance frequency component is lost. As a result, the NG detector 218 will not detect oscillations at node V1, as shown in FIG. 4B, and, therefore, will trigger the switch driver 220.

If a line-to-ground fault (LG) is present, then the example GFDC 202 may be electrically represented by an LG equivalent circuit 502 as shown in FIG. 5A. In the illustrated LG equivalent circuit 502, current I1 represents a line current fault (which is a function of the imbalance current divided by the number of turns n) directly to ground at a source frequency (e.g., a U.S. domestic frequency of 60 Hertz (Hz)). During such an LG fault, node V1 may still exhibit a signal component at resonance frequency by virtue of the LC tank (i.e., L2 and C1) driven by the negative resistance (−R1). As such, detection of the properties of the signal at the NG detector 218 may not be sufficient to ascertain that a fault has occurred. However, the low pass filter 216 may segregate the relatively higher frequency component leaving lower frequency components (e.g., 60 Hz) at node V2, as shown in FIG. 5B. The magnitude of the signal at line frequency (e.g., 60 Hz), detected by the LG detector 222 may cause the LG detector 222 to signal the switch driver 220, thereby allowing the example GFDC 202 to protect an end-user from a potential shock hazard. Additionally or alternatively, the switch driver may provide a fault indication to a user by driving an indicator lamp, a light-emitting diode (LED), and/or other indicia of a fault condition.

If both an NG fault and an LG fault are simultaneously present, the example GFDC 202 may detect such a condition and signal the switch driver 220, when appropriate. In the illustrated example node output of FIG. 6, the NG detector 218 detects an NG fault by virtue of the signal component at resonance frequency being absent at node V1. Additionally, the LG detector 222 detects an LG fault by virtue of the properties of the signal at node V2 (e.g., an amplitude, a duration, etc.)

FIG. 7 illustrates a flowchart representative of an example process that may be executed to implement the example GFDC 202 illustrated in FIG. 2. The example process of FIG. 7, as well as the example processes of FIGS. 12 and 15 discussed in further detail below, may be implemented using machine readable instructions executed by a processor, a controller, and/or any other suitable processing device. For example, the example processes of FIGS. 7, 12, and 15 may be embodied in coded instructions stored on a tangible medium such as a flash memory, or RAM associated with a processor (e.g., a controller, a microprocessor, a DSP). Alternatively, some or all of the example processes shown in the flowcharts of FIGS. 7, 12, and 15 may be implemented using an application specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable logic device (FPLD), discrete logic, hardware, firmware, etc. Also, some or all of the example processes of FIGS. 7, 12, and 15 may be implemented manually or as combinations of any of the foregoing techniques, for example, a combination of firmware and/or software and hardware may be implemented using circuits based on passive or active circuit components such as resistors, capacitors, inductors, operational amplifiers, etc.

Further, although the example processes of FIGS. 7, 12, and 15 are described with reference to the flowcharts of FIGS. 7, 12, and 15, persons having ordinary skill in the art will readily appreciate that many other methods of implementing the example GFDC 202, the example GFDC 802, the example GFDC 902, the example ground fault interrupter 1000, the example GFDC 1300, and/or the example circuits 1400 and 1450, respectively, illustrated in FIGS. 2, 8A, 9, 10, 13, 14A and 14B may be employed. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, sub-divided, or combined. Additionally, persons of ordinary skill in the art will appreciate that the example processes of FIGS. 7, 12, and 15 be carried out sequentially and/or carried out in parallel by, for example, separate processing threads, processors, devices, circuits, etc.

The example process 700 of FIG. 7 begins with, for example, the NG detector 218 monitoring node V1 for the presence of a signal (block 702). If the NG detector 218 does not detect a signal at the resonance frequency, the example LG detector 222 may determine whether the output signal from the low pass filter 216 is within appropriate thresholds (block 710). The example NG detector 218 may then trigger the gate driver 220 as a condition indicative of an NG fault (block 704). On the other hand, if the NG detector 218 detects a signal at node V1, NG detector 218 may determine whether the detected signal is within acceptable threshold boundaries (block 706). For example, temperature fluctuations may result in oscillation frequency variation of the example virtual inductor 214 that are deemed to be within acceptable limits. Additionally or alternatively, the NG detector 218 may determine if the properties of the signal are within acceptable limits, and trigger the gate driver 220 if not (block 704).

Even if the NG detector 218 detects a signal at node V1 (block 702), and the signal is within acceptable threshold limits (block 706), the LG detector 222 may monitor for a signal after the low pass filter 216 at node V2 (block 708). As described above, the example low pass filter 216 attenuates the oscillation frequency component caused by the parallel combination of L1, C1, −R1, and the inductor L2 (e.g., the virtual inductor 214). In the absence of the oscillation frequency, the LG detector 222 may determine whether a relatively lower frequency is present, such as a frequency at or near the source of a household power line (e.g., 50 Hz, 60 Hz, etc.) (block 710). Without limitation, the example LG detector 222 may determine whether the output signal from the low pass filter 216 is within appropriate thresholds (e.g., magnitude, duration, etc.) (block 710). If not, the LG detector 222 signals the gate driver 220 to trip so that the example GFDC 202 stops providing electrical energy to the load (block 712). However, if the LG detector 222 determines that the signal properties are within the established limits (block 710), then no fault has occurred and the example process 700 continues to monitor nodes V1 and V2 for both NG and LG faults.

FIG. 8A illustrates an additional example GFDC 802 to detect LG and NG faults with one coil rather than two. In the illustrated example of FIG. 8, the GFDC 802 may operate instead of the ground fault detector circuit 116 and corresponding second coil 120 of FIG. 1. The GFDC 802 receives signals from a sense coil 804 having a primary winding through which a line conductor 806 and a neutral conductor 808 pass. Current imbalances between the line conductor 806 and the neutral conductor 808 may be detected by the example sense coil 804 during fault conditions, in which fault conditions include an LG fault and/or an NG fault.

The sense coil 804 includes a secondary winding L1 that is connected to an oscillator S1, and a current-to-voltage amplifier 810 via a saturation capacitor CS to prevent and/or minimize amplifier saturation during DC conditions. However, the example GFDC 802 of FIG. 8A may employ methods and apparatus to eliminate CS while preserving saturation prevention functionality, as discussed in further detail below. The example GFDC 802 also includes a low pass filter 812, an NG detector 814, and an LG detector 816. Both the NG detector 814 and the LG detector 816 may provide one or more signals to a driver 818 in the event of a fault. Persons having ordinary skill in the art will appreciate that the driver 818 may include, but is not limited to, an SCR driver, a transistor driver, a relay driver, etc.

If there are no faults (either LG and/or NG), then a corresponding non-fault equivalent circuit 850 results, as shown in FIG. 8B. Generally speaking, based on the secondary winding L1, which is the magnetization inductance of the sense coil 804, and the frequency of the oscillator S1, the current into the current to voltage amplifier 810 may be represented by Equation 4.

I = V OSC L 1 * 2  π   f ( Equation   4 )

In example Equation 4 above, the value VOSC represents the voltage of oscillator S1, L1 is the magnetization inductance of the sense coil 804, and f is the applied frequency of the oscillator S1. Absent any fault condition, the NG detector 814 may determine that the current is within one or more appropriate thresholds. However, in the event of a NG fault, a corresponding NG fault equivalent circuit 852 results, as shown in FIG. 8C. In the example NG fault equivalent circuit 852 of FIG. 8C, R2 represents an equivalent resistance based on a NG resistance RG and a number of turns (n) in the sense coil 804, mathematically represented in example Equation 5.

R2=n2*RG  (Equation 5)

As a result, the current detected by the current to voltage amplifier 810 is mathematically represented in example Equation 6.

I ≈ V OSC R G  

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