FIELD OF THE INVENTION
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Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for multi-layered memory protection with data redundancy implementing, for example, third dimensional memory technology.
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OF THE INVENTION
Traditional storage technologies, such as hard disk drive technologies (HDD), have used memory protection techniques to preserve file directories and access pointer systems, including file allocation tables (FATs) such as the kind used in a computer software operating system, such as the Disk Operating Systems (DOS), for example. Those pointers, directories, and tables are very valuable data which might be lost in the event of a system failure. In that some data is more important than other data, it is important to protect important data in the event of a system failure, a HDD crash, or the like. In some applications, user data is also important and needs to be protected. Further, protection of data in some storage systems requires reliable hardware components that remain resilient throughout extensive usage. Regardless, in a HDD a head media failure (“head crash”), once it occurs, is a catastrophic failure that is usually irrecoverable. Therefore, there are data redundancy issues and concerns that must be addressed in order to provide data protection.
Some of the approaches to memory protection have been applied to non-volatile memory, such as flash memory, which can provide a higher data storage density at a lower cost. However, using flash memory has a few drawbacks. First, flash memory typically performs an erase operation prior to any write operation. Second, additional circuitry is required to implement the erase operation. The additional circuitry increases die area and the cost per bit. Third, flash memory usually requires additional file management software that must be mapped on top of the standard file management structure in order to perform the erase operation (e.g., a block erase operation).
As non-volatile memory technologies continue to encroach into the data storage arena and displace traditional HDD's in applications such as RAID systems and solid state drives (SSD's), it is desirable to implement data redundancy in non-volatile memory and to eliminate the latency created by the erase before write operation and its associated file system overhead (e.g., FLASH OS).
There are continuing efforts to improve data redundancy technology for protecting data stored in memory.
BRIEF DESCRIPTION OF THE DRAWINGS
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Various examples are disclosed in the following detailed description and the accompanying drawings, in which:
FIG. 1 depicts an apparatus implementing a redundancy circuit configured to duplicate data associated with multiple layers of memory;
FIG. 2 is a block diagram depicting an example of a redundancy circuit;
FIG. 3A depicts a cross-sectional view of an example of an integrated circuit implementing a redundancy circuit;
FIG. 3B depicts a cross-sectional view of another example of an integrated circuit implementing a redundancy circuit;
FIG. 3C depicts a cross-sectional view of yet another example of an integrated circuit implementing a redundancy circuit;
FIG. 4 is a diagram depicting a cross-sectional view of a partial duplication for use with a redundancy circuit;
FIG. 5A is a block diagram depicting one example of an integrated circuit implementing a redundancy circuit;
FIG. 5B is a block diagram depicting one example of an integrated circuit implementing data redundancy in a third dimensional memory array with specific memory planes allocated for storing read data and different memory planes allocated for storing copy data;
FIG. 5C is a block diagram depicting one example of an integrated circuit implementing full data redundancy in different planes of a third dimensional memory array;
FIG. 6 depicts an illustration of an exemplary parity module;
FIG. 7A depicts an example of memory cells positioned in a two-terminal cross-point array;
FIG. 7B depicts a single layer or multiple vertically stacked layers of memory arrays formed BEOL on top of a base layer die including circuitry formed FEOL;
FIG. 7C depicts one example of a vertically stacked memory including multiple array layers that share conductive array lines and formed BEOL directly on top of a previously formed FEOL base layer;
FIG. 8A depicts a cross-sectional view of an integrated circuit die including a single layer of memory fabricated over a substrate including active circuitry fabricated on the substrate in a logic layer;
FIG. 8B depicts a cross-sectional view of an integrated circuit die including vertically stacked layers of memory fabricated over a substrate including active circuitry fabricated on the substrate in a logic layer;
FIG. 8C depicts an integrated circuit die including vertically stacked layers of memory with shared conductive array lines fabricated over a substrate including active circuitry fabricated on the substrate in a logic layer;
FIG. 9 depicts a memory system including a non-volatile two-terminal cross-point array;
FIG. 10 depicts an exemplary electrical system that includes at least one non-volatile two-terminal cross-point array; and
FIG. 11 depicts top plan views of a wafer processed FEOL to form a plurality of base layer die including active circuitry and the same wafer subsequently processed BEOL to form one or more layers of memory directly on top of the base layer die where the finished die can subsequently be singulated, tested, and packaged into integrated circuits.
Although the previous drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the FIGS. are not necessarily to scale.
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U.S. patent application Ser. No. 11/095,026, filed Mar. 30, 2005, entitled “Memory Using Mixed Valence Conductive Oxides,” and published as U.S. Pub. No. US 2006/0171200 A1 on Aug. 3, 2006, is herein incorporated by reference in its entirety and for all purposes, and describes non-volatile third dimensional memory elements that may be arranged in a two-terminal, cross-point memory array. The memory elements can be a component of a memory cell that includes electrically in series with the memory element, other structures including but not limited to a non-ohmic device (NOD) and electrodes. New non-volatile memory structures are possible with the capability of this third dimensional memory array. The technology allows for the emulation of other memory technologies by duplicating the interface signals and protocols, while accessing the third dimensional memory array. The third dimensional memory array may emulate other types of memory (e.g., DRAM, SRAM, FLASH, and ROM), providing memory combinations (e.g., DRAM, FLASH, and SRAM) within a single component. In at least some embodiments, a two-terminal memory cell can be configured to change conductivity when exposed to an appropriate voltage drop across the two-terminals. The memory cell can include an electrolytic tunnel barrier and a mixed valence conductive oxide (e.g., a memory element) in some embodiments, as well as multiple mixed valence conductive oxide structures in other embodiments. A voltage drop across the electrolytic tunnel barrier can cause an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions out of the mixed valence conductive oxide, according to some embodiments.
In some embodiments, an electrolytic tunnel barrier and one or more mixed valence conductive oxide structures do not need to operate in a silicon substrate, and, therefore, can be fabricated (e.g., back-end-of-the-line BEOL) above circuitry being used for other purposes (e.g., circuitry fabricated front-end-of-the-line FEOL). The circuitry portion of an IC can be fabricated FEOL on a substrate (e.g., a silicon Si wafer) that is partitioned into die with each die forming the base structure for the IC. After the FEOL processing is completed the substrate is processed BEOL to fabricate the one or more layers of memory directly on top of each FEOL die. An inter-level interconnect structure formed FEOL serves as the structural and electrical foundation for the subsequent formation of the one or more layers of memory that will be deposited (e.g., formed) on top of the FEOL die. The inter-level interconnect structure includes vias, plugs, damascene structures or the like, that allow the FEOL circuitry to be electrically coupled with the BEOL memory layer(s). After BEOL processing is completed, the finished die can be singulated from the substrate (e.g., removed by sawing or cutting) to form individual die that can be inserted into a suitable package and electrically coupled with bonding pads or other structures in the package to form an integrated circuit (IC). Therefore, each die is an integral unit that includes at a bottommost layer the FEOL circuitry and upper layers comprised of one or more layers of third dimensional memory that are positioned above the FEOL circuitry layer. Unlike conventional IC\'s that have conventional memory (e.g., SRAM, DRAM, and FLASH) fabricated FEOL on the same substrate die as the circuitry that accesses the memory such that the memory and the circuitry are disposed on the same physical plane, the BEOL third dimensional memory layer(s) are not on the same plane as the FEOL circuitry and therefore do not take up area on the FEOL die. Accordingly, data storage can be increased without increasing the area of the FEOL die by fabricating additional BEOL memory layers on top of the FEOL die (e.g., along the +Z axis of FIGS. 7B-8C).