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Bus-handling




Title: Bus-handling.
Abstract: A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state. ...


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USPTO Applicaton #: #20100146169
Inventors: Victor Flachs


The Patent Description & Claims data below is from USPTO Patent Application 20100146169, Bus-handling.

FIELD OF THE INVENTION

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The present invention relates generally to communications and specifically to wake-up procedures of communication devices.

BACKGROUND

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Many computerized systems, such as portable computers, are battery operated and measures are taken to reduce their power consumption. One method used to reduce power consumption is shutting down units which are not currently in use. The unit which is shut down generally disables its clock and waits for a signal instructing it to wake up, i.e., to enter an active mode.

US patent publication 2008/0178026 to Chen, titled: “Computer System and Power Saving Method Thereof”, the disclosure of which is incorporated herein by reference, describes a system in which when a chipset and a processor are in a power saving mode a bus connecting the chipset and processor is disabled. When the chipset needs to send data to the processor it enables the bus, transmits the data and then moves back to the sleep state.

EP patent 1 594 253 to Bogavac Davor, titled: “Method and Device to Wake-up Nodes in a Serial Databus”, the disclosure of which is incorporated herein by reference, describes another system with nodes that wake up responsive to transmissions from a master unit, each unit waking up only for specific transmissions directed to it.

The waking up process may take time, referred to as a “wake up latency”. In some cases, the source of transmitted data is not aware that the receiving unit is asleep and the sleeping unit is configured to wake up immediately when it identifies that signals are being transmitted on the bus. If the wake up latency is not sufficiently short, however, the sleeping unit will wake up only after at least part of the data from the source was transmitted and the transmission will be lost. While some sources may be configured to receive retransmission requests, other sources may not be so adapted and the data they transmit is permanently lost if the receiving unit does not awake fast enough.

U.S. Pat. No. 7,363,523 to Kurts et al., titled: “Method and Apparatus for Controlling Power Management State Transitions”, the disclosure of which is incorporated herein by reference, suggests having a plurality of low power states for a processor, involving different extents of processor units shut down. When a bus signal is received, the processor does not move to a full scale operation state, but rather moves to an intermediate operation state which is sufficient to handle the bus access. The transition to the intermediate state is performed within 35 microseconds.

U.S. Pat. No. 7,039,819 to Kommrusch et al., titled: “Apparatus and Method for Initiating a Sleep State in a System on a Chip Device”, the disclosure of which is incorporated herein by reference, suggests a state having a wake latency of about 1 microsecond.

Some processors, however, may not be able to wake up with a short enough latency, to catch the beginning of data transmitted on the bus.

US patent publication 2007/0239920 to Frid, titled: “Method and System for Communication Between a Secondary Processor and an Auxiliary Display Subsystem of a Notebook”, the disclosure of which is incorporated herein by reference, suggests including a low power auxiliary display in a portable computer, which can be used instead of waking up the main processor and display of the computer. This solution, however, still requires substantial power amounts for the auxiliary display, and it would be desired to have a sleep state also for the auxiliary display in order to further reduce power consumption.

U.S. Pat. No. 6,892,332 to Gulick, titled: “Hardware Interlock Mechanism Using a Watchdog Timer”, the disclosure of which is incorporated herein by reference, describes a system in which wake-ups are performed periodically and not responsive to external signals. Such a system is susceptible both to unnecessary wake ups and to delayed responses to external requests.

SUMMARY

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OF THE INVENTION

An aspect of some embodiments of the present invention relates to a bus monitoring unit, which is adapted to identify transmissions on the bus and to stall the bus responsive thereto in order to prevent transmissions thereon, until a device serviced by the bus monitoring unit is prepared to receive the transmissions.

In some embodiments of the invention, in addition to stalling the bus, the bus monitoring unit initiates a wake up of the serviced device, responsive to identifying the transmission on the bus.

When the serviced device is awake, the bus is released from the stalling. In some embodiments of the invention, before releasing the bus, the bus monitoring unit notifies the serviced device that it was stalled during a transmission, so that the serviced device adjusts itself to continue receiving the transmission that was stopped in the middle when the bus was stalled.

Alternatively or additionally, the bus monitoring device provides the serviced device with signals which imitate the beginning of a transmission which was missed while the serviced device was in the sleep mode, before the bus was stalled.

There is therefore provided in accordance with an exemplary embodiment of the invention, a processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive, a communication port adapted to receive signals from external units over a bus, which is configured not to be fully operative in the sleep state and a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state.

Optionally, the bus monitoring unit is configured to provide a wakeup signal to the processing unit, responsive to identifying a transmission on the bus that is directed to the communication port. Optionally, the bus monitoring unit is configured to provide the wakeup signal and to stall the bus, substantially concurrently. Alternatively, the bus monitoring unit is configured to provide the wakeup signal before stalling the bus. Optionally, the bus monitoring unit comprises an asynchronous unit which identifies transmissions on the bus without use of a time signal. Optionally, the bus monitoring unit comprises a synchronous unit which identifies transmissions on the bus using a time signal. Optionally, the bus monitoring unit is configured to provide the communication port with an imitation of a beginning portion of a transmission from an external unit, before releasing the bus.

There is further provided in accordance with an exemplary embodiment of the invention, a method of handling transmissions, comprising identifying a transmission received over a bus, while a port intended to receive the transmission is in a sleep state, moving the port into an operative state and stalling the bus responsive to receiving the transmission, until the port is in the operative state. Optionally, the method includes notifying the port, when it is in the operative state, that a transmission began whilst said port was in the sleep state and/or locally providing an imitation of a beginning of the identified transmission to the port, after it moves into the operative state, before terminating the stalling of the bus.

BRIEF DESCRIPTION OF THE FIGURES

With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention; the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice. In the accompanying drawings:

FIG. 1 is a schematic illustration of an embedded controller connected to an external unit via a bus, in accordance with an embodiment of the invention;

FIG. 2 is a state diagram of an embedded controller, in accordance with an exemplary embodiment of the invention; and

FIG. 3 is a schematic illustration of signals transmitted on a bus, in accordance with an exemplary embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Overview

FIG. 1 is a schematic illustration of an embedded controller (EC) 100 connected over a bus 110 to an external unit 150, in accordance with an embodiment of the invention. Embedded controller 100 may be employed, for example, in a notebook computer, to perform control tasks of one or more peripherals, such as a keyboard, a mouse, a screen, a power supply and/or a battery (not shown). Embedded controller 100 includes a processing unit core 102 which manages its operation, and a clock signal generator 104, which provides a timing signal to the various sub-sections (not all of which are shown) of embedded controller 100. Controller 100 further includes an SM Bus port 106, which communicates with one or more external units 150, via bus 110.

In order to reduce power consumption, embedded controller 100 is configured to have a sleep state in which clock signal generator 104 is shut down. A start signal identifier 108 is configured to monitor the signals transmitted on bus 110 while EC 100 is in the sleep state. When in full operation, port 106 optionally handles detection of transmissions on its own and signal identifier 108 is not in use. When a transmission on bus 110 is identified, signal identifier 108 optionally sends a wake up signal 126 to clock 104 and in parallel stalls the transmission on bus 110, until port 106 is ready to receive the transmission, as is now described in detail.

FIG. 2 is a state diagram of EC 100, in accordance with an exemplary embodiment of the invention. When not active, EC 100 enters a sleep state 200 in which it consumes very little or; no power. When a transmission on bus 110 is identified 202, signal identifier 108 stalls 206 bus 110 and optionally, in parallel or immediately thereafter, sends 204 a wake up signal to clock generator 104. Responsive to the wake up signal, EC 100 undergoes a wake up procedure 208. At the end of the wakeup procedure, signal identifier 108 releases 212 the bus and allows EC 100 to handle the incoming transmission and EC 100 enters a work state 210. When EC 100 is in work state 210 but it is determined 214 that it can be moved to the sleep state in order to reduce power consumption, EC 100 undergoes a prepare-to-sleep procedure 216 and moves into sleep state 200.

Identification

Referring in detail to identifying (202) a transmission on bus 110, in some embodiments of the invention, bus 110 is governed by a protocol which requires transmission of a predetermined start signal before transmitting data, and the identifying (202) involves identifying at least a portion of the start signal. In some embodiments of the invention, the identification is performed based on the signals on fewer than all the lines of the bus, for example on only a single line, such as only on the data line or only on the clock line of the bus. The extent of the portion to be identified is optionally selected during a design stage, based on a tradeoff between the competing requirements of more accurate identification and of minimizing the resources required for the identification.




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stats Patent Info
Application #
US 20100146169 A1
Publish Date
06/10/2010
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
/
Drawings
0




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Electrical Computers And Digital Data Processing Systems: Input/output   Intrasystem Connection (e.g., Bus And Bus Transaction Processing)   Protocol  

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20100610|20100146169|bus-handling|A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is |Nuvoton-Technology-Corporation
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