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Prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices




Title: Prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices.
Abstract: A method of fabricating a semiconductor device begins by forming a lower interconnection dielectric on a substrate and forming at least one active or passive device in the lower interconnection dielectric. An etch stop layer is formed on the lower interconnection dielectric and an interconnect stack layer is formed on the etch stop layer. At least one interconnect trench structure and at least one crack stop trench are etched in the interconnect stack layer while maintaining electrical isolation between the interconnect structure and the crack stop trench. ...

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USPTO Applicaton #: #20100096699
Inventors: Koji Miyata


The Patent Description & Claims data below is from USPTO Patent Application 20100096699, Prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices.

STATEMENT OF RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 11/404,738, filed Apr. 14, 2006, entitled “Prevention of Plasma Induced Damage Arising From Etching of Crack Stop Trenches in Multi-Layered Low-K Semiconductor Devices”, which is incorporated in its entirety by reference herein.

FIELD OF THE INVENTION

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The present invention relates generally to dual damascene interconnections for integrated circuits, and more specifically to a dual damascene interconnection having a low k layer with trenches to prevent cracking.

BACKGROUND

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OF THE INVENTION

The manufacture of integrated circuits in a semiconductor device involves the formation of a sequence of layers that contain metal wiring. Metal interconnects and vias which form horizontal and vertical connections in the device are separated by insulating layers or inter-level dielectric layers (ILDs) to electrically isolate wires from each other and to prevent crosstalk between the metal wiring that can degrade device performance. A popular method of forming an interconnect structure is a dual damascene process in which vias and trenches are filled with metal in the same step to create multi-level, high density metal interconnections needed for advanced high performance integrated circuits. The most frequently used approach is a via first process in which a via is formed in a dielectric layer and then a trench is formed above the via. Recent achievements in dual damascene processing include lowering the resistivity of the metal interconnect by switching from aluminum to copper, decreasing the size of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of insulators or ILDs by using so-called low k materials to avoid capacitance coupling between the metal interconnects. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9. One class of low-k material that have been explored are organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD.

One difficulty that arises when the dielectric layers are formed from low-k materials is that the reduced strength of the low-k materials, in combination with thinner layers, frequently results in cracking when such materials are subjected to mechanical and thermal stresses. Typical low-k materials in use have included carbon doped silicon dioxide such as commercially available Black Diamond™ and other materials that tend to be porous, thereby reducing the overall dielectric constant. Porous low-k materials have a drawback in that the porosity tends to weaken the overall strength and hardness of the material making crack initiation and propagation more likely. As the requirement for device density increases, the number of levels in an integrated circuit structure has increased to 4 to 10 or more levels. The increased number of material layers contributes to the buildup of compressive and tensile stresses in the multiple layers, especially when subjected to thermal and mechanical stresses, which frequently do not offset one another. The result is that cracking becomes more likely as the number of layers increase and the process wafer is subjected to externally induced stresses that arise when the wafer is cut into the individual dies.

One known approach to alleviate these stresses is to provide crack stop trenches that are located at the die edge to prevent cracking of the die. The crack stop trench also prevents the diffusion of moisture into the device and thus it is also sometimes referred to as a moisture block trench or simply a moisture block. The crack stop trenches are generally formed simultaneously with the trenches and vias of the metal interconnects. That is, the same lithographic steps used in forming the interconnects, including patterning, etching of the pattern, removal of the mask, and etching of the interconnect trenches, are generally used to form the crack stop trenches.

The etching of the trenches is typically performed by reactive ion etching. During this process a plasma is generated that gives rise to currents in the trenches as they are being etched. Unfortunately, the currents that are generated can produce voltages that damage the active or passive devices located in the integrated circuit. This damage, so-called plasma-induced damage, degrades the operational characteristics of the resulting device.

Accordingly, it would be desirable to provide a method for reducing plasma-induced damage that can arise during formation of single and dual damascene interconnect structures that employ crack stop trenches.

SUMMARY

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OF THE INVENTION

In accordance with the present invention, a method of fabricating a semiconductor device begins by forming a lower interconnection dielectric on a substrate and forming at least one active or passive device in the lower interconnection dielectric. An etch stop layer is formed on the lower interconnection dielectric and an interconnect stack layer is formed on the etch stop layer. At least one interconnect trench structure and at least one crack stop trench are etched in the interconnect stack layer while maintaining electrical isolation between the interconnect structure and the crack stop trench.

In accordance with one aspect of the invention at least one electrically isolating region is formed in the lower interconnection dielectric below a location where the crack stop trench is to be etched.

In accordance with another aspect of the invention, the electrically isolating region comprises a gate dielectric layer.

In accordance with another aspect of the invention, the etching is a reactive ion etching process.

In accordance with another aspect of the invention, the substrate is a SOI substrate.

In accordance with another aspect of the invention, the SOI substrate includes a buried oxide layer that serves as an electrically isolating region that facilitates maintenance of the electrical isolation between the interconnect structure and the crack stop trench during etching.

In accordance with another aspect of the invention, the crack stop trench is continuous and surrounds the interconnect stack layer.

In accordance with another aspect of the invention, the interconnect stack layer comprises a low k dielectric material.

In accordance with another aspect of the invention, the low k dielectric material includes an organosilicon material.

In accordance with another aspect of the invention, the etch stop layer is formed of at least one of SiC, SiN, and SiCN.

In accordance with another aspect of the invention, the dielectric material is formed using chemical vapor deposition.

In accordance with another aspect of the invention, a capping layer is formed on the interconnect stack layer.

In accordance with another aspect of the invention, the capping layer is formed of at least one of SiO2, SiOF, SiON, SiC, SiN and SiCN.

In accordance with another aspect of the invention, a semiconductor wafer is provided. The wafer includes a lower interconnection dielectric located on a substrate, at least one active or passive device formed in the lower interconnection dielectric and at least one electrical isolating region formed in the lower interconnection dielectric. An etch stop layer is located over the lower interconnection dielectric and an interconnect stack layer is located over on the etch stop layer. At least one interconnect trench structure is located in the interconnect stack layer at least one crack stop trench is located in the interconnect stack layer over the electrical isolating region.

In accordance with another aspect of the invention, the crack stop trenches are continuous and extend around a periphery of an individual die area.

BRIEF DESCRIPTION OF THE DRAWINGS

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FIG. 1 shows a plan view of a conventional semiconductor wafer.

FIG. 2 shows a partial cross-sectional view through semiconductor wafer of FIG. 1.

FIG. 3 shows another partial cross-sectional view through semiconductor wafer of FIG. 1 to illustrate plasma induced damage that can arise during reactive ion etching.

FIGS. 4-6 show various partial cross-sectional views through a semiconductor wafer constructed in accordance with the present invention.

FIGS. 7-13 show the process steps involved in an exemplary process flow used to form a semiconductor wafer in accordance with the present invention.




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stats Patent Info
Application #
US 20100096699 A1
Publish Date
04/22/2010
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
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Drawings
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20100422|20100096699|prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices|A method of fabricating a semiconductor device begins by forming a lower interconnection dielectric on a substrate and forming at least one active or passive device in the lower interconnection dielectric. An etch stop layer is formed on the lower interconnection dielectric and an interconnect stack layer is formed on |Sony-Electronics-Inc