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Semiconductor device and fabrication method thereof


Title: Semiconductor device and fabrication method thereof.
Abstract: To solve these problems, a method of fabricating a semiconductor device according to the present invention comprises the steps of forming a hydrogen-containing first insulating film on a semiconductor layer formed into a predetermined shape, conducting heat-treatment in a hydrogen atmosphere or in an atmosphere containing hydrogen formed by plasma generation, forming a second insulating film in contact with the first insulating film, conducting heat-treatment in a hydrogen atmosphere or in an atmosphere containing hydrogen formed by plasma generation, forming a hydrogen-containing third insulating film on the second insulating film and conducting heat-treatment in an atmosphere containing hydrogen or nitrogen. A hydrogenation method that utilizes plasma directly exposes a crystalline semiconductor film to the plasma, and therefore involves the problem that the crystalline semiconductor film is damaged by the ions generated simultaneously in the plasma. If a substrate is heated to 400° C. or above to recover this damage, hydrogen is re-emitted from the crystalline semiconductor film. ...

Browse recent Semiconductor Energy Laboratory Co., Ltd. patents
USPTO Applicaton #: #20100035424 - Class: $ApplicationNatlClass (USPTO) -
Inventors: Shunpei Yamazaki, Taketomi Asami, Hidehito Kitakado, Yasuyuki Arai



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The Patent Description & Claims data below is from USPTO Patent Application 20100035424, Semiconductor device and fabrication method thereof.

BACKGROUND OF THE INVENTION

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1. Field of the Invention

This invention relates to a semiconductor device having an active circuit constituted by thin film transistors formed over a substrate, and a method of fabricating the semiconductor device. More particularly, this invention can be used appropriately for fabricating thin film transistors using a crystalline semiconductor layer. The present invention can be utilized also for fabricating an integrated circuit that comprises thin film transistors, an electro-optical device typified by an active matrix display device, and an image sensor, and an electronic appliance having the electro-optical device mounted thereto.

2. Description of the Related Art

A semiconductor device typified by an active matrix liquid crystal display device comprising a large number of thin film transistors (TFTs) arranged on a substrate has been developed. In order to accomplish high mobility in the TFTs, it has been believed preferable to use a crystalline semiconductor film for a semiconductor layer. Most of polycrystalline semiconductors that are utilized for the TFT are formed by crystallization technologies such as laser annealing and thermal annealing. However, because a large number of defects exist in the crystalline semiconductor film so crystallized, mobility of the carriers and the life time are markedly lowered with the result that electric characteristics of the TFT are adversely affected.

To eliminate the defects inside the crystalline semiconductor film and an inter-layer insulating film, a hydrogenation process has been known as one of the effective means. The hydrogenation process includes a plasma hydrogenation process that neutralizes the defects by generating hydrogen plasma, and a hydrogenation method that executes heat-treatment in a hydrogen atmosphere. These hydrogen process steps are appropriately incorporated in the fabrication process steps of the TFT.

According to the hydrogenation process utilizing the plasma, however, the crystalline semiconductor film is directly exposed to the plasma in order to effectively introduce hydrogen. In consequence, there remains the problem that the crystalline semiconductor film is damaged by the ions that are formed simultaneously in the plasma. To recover this damage, heat-treatment at 400 to 600° C. is believed necessary, but when heating is made to 400° C. or above, hydrogen is re-emitted from the crystalline semiconductor film. If any atmospheric components such as nitrogen and oxygen remain in the atmosphere in the plasma hydrogenation method, these elements, too, are converted to the plasma and contaminate the crystalline semiconductor film.

When the plasma hydrogenation method is carried out from the surface side of an inter-layer insulating film formed on a gate electrode, the defects existing inside the crystalline semiconductor film can be neutralized to a certain extent. However, the hydrogen concentration introduced into the film by this method has a distribution such that it progressively decreases from the surface to its inside. For this reason, it has been difficult to sufficiently hydrogenate the crystalline semiconductor film on the lower layer side. The heat-treatment process in the hydrogen atmosphere as another method involves the problem that the process time gets unavoidably extended in order to improve the hydrogenation effect.

SUMMARY

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OF THE INVENTION

The present invention is directed to provide a high performance semiconductor device that can solve the problems described above, and can be efficiently processed by a hydrogenation process without imparting damage and contamination of a crystalline semiconductor film, and a method of fabricating such a semiconductor device.

A method of fabricating a semiconductor device according to the present invention comprises the steps of forming a hydrogen-containing first insulating film over a semiconductor layer that is formed into a predetermined shape over a substrate, and then conducting heat-treatment in a hydrogen atmosphere or in an atmosphere containing hydrogen that is formed by generating hydrogen plasma. The first insulating film may be an inter-layer insulating film formed over a gate electrode. When hydrogenation is carried out through this first insulating film, the problems of damage to a semiconductor layer and its contamination can be avoided. Because hydrogen is supplied to the hydrogen-containing first insulating film, hydrogen in this first insulating film diffuses into its lower layer and hydrogenation of the semiconductor layer proceeds.

Another method of fabricating a semiconductor device according to the present invention comprises the steps of forming a hydrogen-containing first insulating film over a semiconductor layer that is formed into a predetermined shape over a substrate, forming a second insulating film in close contact with the first insulating film, and then executing heat-treatment in a hydrogen atmosphere or in an atmosphere containing hydrogen that is formed by plasma generation. Hydrogen that is supplied from the surface of the second insulating film diffuses into the first insulating film, and hydrogen in the first insulating film diffuses into the lower layer, so that the semiconductor layer can be hydrogenated. In this case, the heat-treatment may be carried out in the hydrogen atmosphere or in the atmosphere containing hydrogen formed by plasma generation, after the first insulating film is formed.

Another method of fabricating a semiconductor device according to the present invention comprises the steps of forming a hydrogen-containing first insulating film over a semiconductor layer that is formed into a predetermined shape over a substrate, conducting then heat-treatment in a hydrogen atmosphere or in an atmosphere containing hydrogen formed by plasma generation, forming a hydrogen-containing third insulating film on the first insulating film, and conducting heat-treatment in an atmosphere containing hydrogen or nitrogen. When the third insulating film comprises a compact film of a silicon nitride oxide or a silicon nitride film, the quantity of hydrogen dissociating from the first insulating film into the gaseous phase can be reduced and hydrogenation of the semiconductor layer can be attained more reliably.

More preferably, the method of fabricating a semiconductor device comprises the steps of forming a hydrogen-containing first insulating film over a semiconductor layer formed into a predetermined shape over a substrate, conducting then heat-treatment in a hydrogen atmosphere or in an atmosphere containing hydrogen that is formed by plasma generation, forming a second insulating film in contact with the first insulating film, conducting heat-treatment in a hydrogen atmosphere or in an atmosphere containing hydrogen formed by plasma generation, and conducting heat-treatment in an atmosphere containing hydrogen or nitrogen after the hydrogen-containing third insulating film is formed on the second insulating film. According to this construction, hydrogen that is supplied by the step of conducting the heat-treatment in the hydrogen atmosphere or in the atmosphere containing hydrogen formed by plasma generation diffuses into the lower layer, and hydrogenation of the semiconductor layer can be effected reliably.

The first insulating film is preferably a silicon nitride oxide film made from silane, nitrous oxide or ammonia. The second insulating film may be a silicon nitride oxide film made from silane or nitrous oxide. The third insulating film is preferably a silicon nitride oxide film made from silane, nitrous oxide or ammonia, or a silicon nitride film made from silane, ammonia or nitrogen. All the first to third insulating films fabricated in this way have the carbon concentration in the films of not greater than 2×1019 cm−3.

Therefore, the semiconductor device according to the present invention comprises, over a semiconductor layer formed into a predetermined shape, a first insulating film comprising a silicon nitride oxide film having a hydrogen concentration of at least 1 atomic % to less than 30 atomic % and a nitrogen concentration of at least 10 atomic % to less than 25 atomic %, and a third insulating film keeping contact with the first insulating film and comprising a silicon nitride oxide film having a hydrogen concentration of at least 1 atomic % to less than 30 atomic % and a nitrogen concentration of at least 10 atomic % to less than 25 atomic % or a silicon nitride film having a hydrogen concentration of at least 1 atomic % to less than 30 atomic %.

The semiconductor device may comprise, over a semiconductor layer formed into a predetermined shape, a first insulating film comprising a silicon nitride oxide film containing at least 10 atomic % to less than 30 atomic % of hydrogen, and having a nitrogen concentration of at least 10 atomic % to less than 25 atomic %, a second insulating film comprising a silicon nitride oxide film, keeping contact with the first insulating film and having a nitrogen concentration of less than 10 atomic %, and a third insulating film keeping contact with the second insulating film and comprising a silicon nitride oxide film having a nitrogen concentration of at least 1 atomic % to less than 25 atomic % or a silicon nitride film having a hydrogen concentration of at least 1 atomic % to less than 30 atomic %.

In a semiconductor device including a gate insulating film formed in contact with a semiconductor layer shaped into a predetermined shape and a gate electrode formed at a predetermined position on the gate insulating film, a semiconductor device according to the present invention comprises a first insulating film keeping contact with the gate insulating film and with the gate electrode and comprising a silicon nitrogen oxide film containing at least 1 atomic % to less than 30 atomic % of hydrogen and having a nitrogen concentration of at least 10 atomic % to less than 25 atomic %, and a third insulating film keeping contact with the first insulating film and comprising a silicon nitride oxide film having a nitrogen concentration of at least 1 atomic % to less than 30 atomic % and a nitrogen concentration of at least 10 atomic % to less than 25 atomic %, or a silicon nitride film having a hydrogen concentration of at least 1 atomic % to less than 30 atomic %.

In a semiconductor device including a gate insulating film so formed as to keep contact with a semiconductor layer formed into a predetermined shape and a gate electrode formed at a predetermined position on the gate insulating film, a semiconductor device according to the present invention comprises a first insulating film comprising a silicon nitride oxide film so formed as to keep contact with the gate insulating film and with the gate electrode, containing at least 1 atomic % to less than 30 atomic % of hydrogen and having a nitrogen concentration of at least 10 atomic % to less than 25 atomic %, a second insulating film keeping contact with the first insulating film and comprising a silicon nitride oxide film having a nitrogen concentration of less than 10 atomic %, and a third insulating film keeping contact with the second insulating film and comprising a silicon nitride oxide film having a hydrogen concentration of at least 1 atomic % to less than 30 atomic % and a nitrogen concentration of at least 10 atomic % to less than 25 atomic %, or a silicon nitride film having a nitrogen concentration of at least 1 atomic % to less than 30 atomic %.

BRIEF DESCRIPTION OF THE DRAWINGS

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These and other objects and novel features of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a sectional view showing a fabrication process of a TFT;

FIG. 2 is a sectional view showing the fabrication process of the TFT and is a top view of a CMOS circuit;

FIG. 3 is a sectional view showing a fabrication process of an active matrix substrate;

FIG. 4 is a sectional view showing a fabrication process of an active matrix substrate;

FIG. 5 is a sectional view showing a fabrication process of an active matrix substrate;

FIG. 6 is a sectional view of an active matrix type liquid crystal display device;

FIG. 7 is a perspective view of an active matrix substrate;

FIG. 8 is a top view of a pixel matrix circuit and is also a top view of a CMOS circuit;

FIG. 9 is an explanatory view of an embodiment of the present invention;

FIG. 10 is a graph showing the change of a hydrogen concentration in a silicon nitride oxide film due to heat-treatment;

FIG. 11 is a sectional view showing a fabrication process of a TFT;

FIG. 12 is a sectional view showing a fabrication process of a TFT;

FIG. 13 is a sectional view showing a fabrication process of a TFT;

FIG. 14 is a sectional view of a pixel matrix circuit and is its top view;

FIG. 15 is an explanatory view of another embodiment of the present invention;

FIG. 16 is a circuit diagram of an EL panel and is its sectional structural view;

FIG. 17 is a perspective view showing an example of a semiconductor device;

FIG. 18 is a perspective view showing another example of the semiconductor device;

FIG. 19 is a perspective view showing a construction of a projection type liquid crystal display device;

FIG. 20 is a top view and a sectional view showing a construction of an EL display device;

FIG. 21 is a sectional view of a pixel portion of the EL display device;

FIG. 22 is a top view and a circuit diagram of the pixel portion of the EL display device; and

FIG. 23 is a circuit diagram of an example of the pixel portion of the EL display device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be explained with reference to FIG. 9. In FIG. 9(A), underlying films 902 and 903 of a semiconductor layer are constituted by a silicon nitride oxide film on a substrate 901. A semiconductor layer 904 formed into a predetermined shape is formed over the substrate 901. This semiconductor layer uses a crystalline semiconductor film that is formed by crystallizing an amorphous semiconductor film by laser crystallization, thermal crystallization or crystallization using a catalytic element. A gate insulating film 905 is formed in close contact with the semiconductor layer, and a gate electrode 906 is arranged at a predetermined position on the gate insulating film.

A first insulating film is formed by using silicon nitride oxide film 907 in such a fashion as to cover the gate insulating film 905 and the gate electrode 906. This silicon nitride oxide film is formed to a thickness of 0.1 to 0.5 μm by a plasma CVD process using silane (SiH4), nitrous oxide (N2O) and ammonia (NH3) as the starting materials. The silicon nitride oxide film fabricated in this way contains 1 to 30 atomic % of hydrogen and 10 to 25 atomic % of nitrogen, though depending on the substrate temperature at the time of film formation (FIG. 9(B)).

The first hydrogenation step is then carried out preferably. This step is carried out in a hydrogen atmosphere or in an atmosphere containing hydrogen converted to hydrogen plasma. For example, the treatment is carried out in the hydrogen-containing atmosphere at 300 to 550° C., preferably at 350 to 450° C., for 1 to 12 hours. The treatment may also be carried out in an atmosphere of a non-depositing gas such as hydrogen or ammonia at a pressure of 1 to 500 Pa, a substrate temperature of 200 to 500° C., preferably 300 to 450° C., for 5 to 120 minutes.

A second insulating film 908 is formed to a thickness of 100 to 500 nm using a silicon nitride oxide film while keeping a close contact with the first insulating film 907. The silicon nitride oxide film may be fabricated from SiH4 and N2O (FIG. 9(C)). The third insulating film 909 is then formed. The third insulating film is formed from a silicon nitride oxide film or a silicon nitride film using a plasma CVD process, and is preferably a compact film. A plasma hydrogenation treatment may be carried out by introducing hydrogen and ammonia as the second hydrogenation step prior to the formation of the third insulating film. Hydrogen is introduced into the second insulating film by this plasma hydrogenation step. This step can be executed as a continuous step to the formation of the third insulating film by merely selecting an appropriate gas seed. The third hydrogenation step, that is to be executed after the formation of the third insulating film, is preferably a heat-treatment step that is carried out in an atmosphere containing hydrogen or nitrogen at 300 to 550° C. for 1 to 12 hours (FIG. 9(D)).

The silicon nitride oxide film and the silicon nitride film contain about 1 to 30 atomic % of hydrogen. Hydrogen contained in the films forms a Si—H bond and an N—H bond, and the mode of bondage can be observed through FT-IR. This hydrogen can be emitted outside the film by heat-treatment at a temperature of not lower than 300° C. FIG. 10 shows the change of the hydrogen bonds when the silicon nitride oxide film fabricated by the use of SiH4, N2O and NH3 as the starting materials at a substrate temperature of 300 to 400° C. is heat-treated at 500° C. The change of the hydrogen bond can be observed mainly as the decrease of hydrogen forming the Si—H bond before and after the heat-treatment. The change quantity can be estimated as about 10 to about 30%. Presumably, hydrogen atoms having weaker bonding power are successively cut off and are emitted.

Therefore, in the process steps shown in FIGS. 9(A) to (D), hydrogen that is contained in the first, second and third insulating films and hydrogen that is introduced afresh by the hydrogenation treatment are easily allowed to move from the respective regions when the heat-treatment is carried out at a temperature higher than 300° C. A part of such hydrogen can reach the semiconductor layer and can neutralize its defect. At this time, the third insulating film as the uppermost layer preferably comprises a compact film of the silicon nitride oxide film or the silicon nitride film. Such a construction can restrict the emission of hydrogen to the gaseous phase outside films due to the heat-treatment and enhances the hydrogenation effect of the semiconductor layer.

FIG. 15 shows another embodiment of the present invention. Underlying films 1502 and 1503, a semiconductor layer 1504 and a gate insulating film 1505 are formed over a substrate 1501, and a first insulating film 1507 and a third insulating film 1508 are formed over the former. The first insulating film 1507 is a silicon nitride oxide film having a hydrogen content of 1 to 30 atomic % and a third insulating film 1508 is preferably a compact film of a silicon nitride oxide film or a silicon nitride film using a plasma CVD process. A plasma hydrogen treatment for introducing hydrogen or ammonia may be carried out prior to the formation of the third insulating film. Hydrogen is introduced into the first insulating film by the plasma hydrogenation treatment. Thereafter, heat-treatment is carried at 300 to 550° C. for 1 to 12 hours in an atmosphere containing hydrogen or nitrogen, thereby achieving hydrogenation of the semiconductor layer.

The embodiments of the present invention described above diffuse hydrogen from the third insulating film to the second insulating film, from the second insulating film to the first insulating film and from the first insulating film to the semiconductor layer when the hydrogenation treatment and the heat-treatment are conducted. Therefore, this embodiment can effectively accomplish hydrogenation of the semiconductor layer.

EXAMPLES Example 1

An example of the present invention will be explained in detail about an inverter circuit as the basic construction of a CMOS circuit, by way of example, with reference to FIGS. 1 and 2. Referring to FIG. 1(A), underlying films 102 and 103 are shown formed over a substrate 101 having an insulating surface. The underlying film 102 is a nitrogen-rich silicon nitride oxide film having a nitrogen concentration of at least 25 atomic % to less than 50 atomic %, and its thickness is 20 to 100 nm and typically 50 nm. The underlying film 103 is a silicon nitride oxide film having a nitrogen concentration of at least 5 atomic % to less than 25 atomic %, and its thickness is 50 to 500 nm, typically 150 to 200 nm. A first island-like semiconductor film 105, a second island-like semiconductor film 104 and a gate insulating film 106 are formed over the former. The island-like semiconductor films are acquired by separating into an island shape the crystalline semiconductor film that is in turn formed by crystallizing an amorphous semiconductor film by laser crystallization or thermal crystallization, by a known technology. The crystalline semiconductor film is formed hereby from the amorphous semiconductor film by a crystallization method using a catalytic element. Semiconductor materials that can be used hereby include silicon (Si), germanium (Ge), a silicon-germanium alloy and silicon carbide. Compound semiconductors such as gallium arsenic can be used, too. The semiconductor film may be formed to a thickness of 10 to 100 nm, typically 50 nm (FIG. 1(A)).

The amorphous semiconductor film fabricated by the plasma CVD process contains hydrogen in a proportion of 10 to 40 atomic % and neutralizes the defects in the film. However, the major proportion of hydrogen is emitted with the progress of the crystallization process. In consequence, a large number of defects remain in the crystal grain boundary, though the defects in the crystal grains can be decreased.

Channel formation regions of the second and first island-like semiconductor films 104 and 105 and resist masks 107 and 108 are then formed. At this time, a resist mask 109 may also be formed in a region in which wiring is to be later formed. A process step of forming impurity regions 110 and 111 by adding an n type imparting impurity element is carried out. Here, phosphorus (P) is added by ion doping using phosphine (PH3). The concentration of phosphorus added to the impurity regions 110 and 111 is preferably within the range of 1×1016 to 1×1019 atoms/cm3, and is hereby 1×1018 atoms/cm3. A part of this region is to function as an LDD region (FIG. 1(B)).

A Si film 112 having a thickness of 5 to 20 nm, a WN (tungsten nitride) film 113 having a thickness of 100 to 200 nm and a W film 114 having a thickness of 100 to 200 nm are formed over the entire surface of the gate insulating film 106. There is no limitation to the method of forming these films, in particular, and the films can be formed by sputtering, for example. The Si film 112 is formed in order to improve adhesion of the WN film 113 with the base, and the WN film 113 can prevent the Si film 112 from reacting and alloying with the W film 114. Furthermore, the WN film 113 can contribute greatly to the increase of the crystal grain size of the W film 114 and to the decrease of the resistance (FIG. 1(C)).

Next, resist masks 115 to 118 are formed. The resist mask 115 is for forming a gate electrode of a p-channel TFT, and the resist masks 117 and 118 are for forming extension lead wires that are disposed for a gate wiring, a gate bus line and lines around them. The resist mask 116 is so formed as to cover the entire surface of the first island-like semiconductor film 105, and functions as a mask for impeding the addition of the impurity in the next process step. Dry etching is conducted using these resist masks, forming the second gate electrode 119, the gate wiring 121 and the extension wiring 122. These gate electrodes and wiring are formed as the Si film, the WN film and the W film that are formed previously are integrated with one another. Etching may use a chlorine type or fluorine type etchant gas. If any etching residue remains, ashing treatment is preferably made. The resist masks 115 to 118 are left as such, and impurity regions 123 and 124 are formed at a part of the second island-like semiconductor film 104, at which a p-channel TFT is to be formed, by adding a p type imparting impurity element. Boron is selected hereby as the impurity element, and ion doping is conducted using diborane (B2H6). The boron concentration is 2×1020 atoms/cm3. There are thus formed the impurity regions 123 and 124 containing boron in a high concentration as shown in FIG. 1(D).

Next, a first gate electrode 128 of the n-channel TFT is formed by forming resist masks 125 to 127. At this time, the first gate electrode 128 is formed in such a fashion as to overlap with a part of the impurity regions 110 and 111 through the gate insulating film (FIG. 1(E)).

Resist masks 129 to 131 are then formed. A part of the gate insulating film 106 is etched away using the resist masks, exposing a part of the island-like semiconductor layers 104 and 105. The resist mask 130 is formed in such a fashion as to cover the first gate electrode 128 and to overlap with a part of the impurity regions 110 and 111. This portion decides the offset quantity of the LDD region. A process step for forming the first impurity region is carried out by adding an n type imparting impurity element, forming thereby an impurity region 138 to serve as a source region in the n-channel TFT and an impurity region 137 to serve as a drain region. The P concentration in these regions is preferably from 1×1019 to 1×1021 atoms/cm3 and is hereby 1×1020 atoms/cm3. P-doped regions 135 and 136 are also formed at a part of the second semiconductor layer 104 that forms the p-channel TFT in the same impurity concentration (FIG. 2(A)).

A first insulating film 139 of a silicon nitride oxide film is formed over the surfaces of the gate insulating film 106, the first and second gate electrodes 128 and 119, the gate wiring 121 and the extension wiring 122 by a plasma CVD process using SiH4, N2O and NH3. Though the method of forming this film is not particularly limited, it is formed to a thickness of 100 to 500 nm at a substrate temperature of 200 to 400° C. In any case, it is preferred to limit the hydrogen concentration in the film to 1 to 30 atomic % and the nitrogen concentration to 10 to 25 atomic %. Because a gas such as TEOS is not used hereby, the carbon concentration in the film is not higher than 2×1019 cm−3 when measured by a secondary ion mass analysis (SIMS).

Next, a process step for activating the n or p imparting impurity element added in a respective concentration is carried out. This step may be conducted by a thermal annealing method using an electric heating furnace, the aforementioned laser annealing method using the excimer laser or a rapid thermal annealing method (RTA) using a halogen lamp. Here, activation is conducted by the thermal annealing method. The heat-treatment is carried out at 300 to 600° C., preferably at 450 to 550° C., and at 550° C. hereby, for 2 hours in the nitrogen atmosphere. The catalytic element used for the crystallization process remains in the island-like semiconductor layers 104 and 105, but it can be segregated to the P-doped regions 135 to 138 and can be gettered from the channel formation region simultaneously with this heat-treatment.

However, when the heat-treatment is carried out at 550° C., a part of hydrogen in the island-like semiconductor layers 104 and 105 and in the first insulating film 139 is emitted into the gaseous phase. Therefore, the first hydrogenation step is preferably carried out hereby. This step can be carried out in a hydrogen atmosphere of 3 to 100% at 300 to 550° C., preferably at 350 to 450° C., for 1 to 12 hours. Alternatively, the heat-treatment may be carried out in an atmosphere containing hydrogen converted to the plasma, at a temperature of 200 to 500° C. for 5 to 120 minutes. Hydrogen supplied to the first insulating film diffuses and its part reaches the semiconductor layer. Therefore, hydrogenation can be accomplished in this step (FIG. 2(B)).

Next, the second insulating film 140 is formed by the plasma CVD process using SiH4 and N2O as the starting material at a substrate temperature of 200 to 400° C. After a predetermined resist mask is formed, the first and second insulating film 139 and 140 are etched so as to form contact holes reaching the source region and the drain region of the TFT, respectively. Source electrodes 141 and 142 and a drain electrode 143 are then formed. This embodiment uses electrodes having a three-layered structure of a 100 nm-thick Ti film, a 300 nm-thick Al film containing Ti and a 150 nm-thick Ti film acquired by continuous sputtering, as the electrodes, though they are not shown in the drawings.

Next, a process step for forming the third insulating film 144 is carried out. The third insulating film is a silicon nitride oxide film formed from SiH4, N2O and NH3 by the plasma CVD process or a silicon nitride film formed from SiH4, N2 and NH3. The plasma hydrogenation treatment is conducted by introducing N2O, N2, NH3, etc, prior to the formation of the film. Here, hydrogen formed in the gaseous phase as a result of plasma generation is supplied also into the second insulating film. If the substrate is heated in advance to 200 to 500° C., hydrogen is allowed to diffuse into the first insulating film and the lower layer below the first insulating film, thereby achieving the second hydrogenation step. The formation condition of the third insulating film is not particularly limited, but the film is preferably a compact film. Finally, the third hydrogenation step is carried out as the heat-treatment at 300 to 550° C. for 1 to 12 hours in an atmosphere containing hydrogen or nitrogen. At this time, hydrogen diffuses from the third insulating film into the second insulating film, from the second insulating film into the first insulating film and from the first insulating film to the semiconductor layer and in this way, hydrogenation of the semiconductor layer can be accomplished effectively. Hydrogen is also emitted from inside the film into the gaseous phase, but this emission can be prevented to a certain extent if the third film is made of a compact film. Alternatively, the loss of hydrogen can be supplemented by supplying hydrogen into the atmosphere.

After the process steps described above are completed, the p-channel TFT is formed in self alignment while the n-channel TFT is formed in non-self alignment. The channel formation region 150, the first impurity regions 151 and 154 and the second impurity regions 152 and 153 are formed in the n-channel TFT of the CMOS circuit. Regions (GOLD regions) 152a and 153a that overlap with the gate electrode and regions (LDD regions) 152b and 153b that do not overlap with the gate electrode are formed in the second impurity regions, respectively. The first impurity region 151 serves as the source region and the first impurity region 154, as the drain region. On the other hand, the channel formation region 145 and the third impurity regions 146 to 149 are formed in the p-channel TFT. Of the third impurity regions, only boron is added to the regions 147 and 148 that keep contact with the channel formation region, and the regions to which both boron and phosphorus are added are formed in the outside regions 146 and 149. However, because the phosphorus concentration of the regions is about a half of the boron concentration, the regions are substantially of the p type. The third impurity regions 146 and 147 serve as the source region and the third impurity regions 148 and 149, as the drain region (FIG. 2(C)).

FIG. 2(D) is a top view of an inverter circuit. A sectional structure of the TFT portion along a line A-A′, a B-B′ sectional structure of the gate wiring portion and a C-C′ sectional structure of the gate bus line portion correspond to those shown in FIG. 2(C). In the present invention, the gate electrode, the gate wiring and the gate bus line are made of the first conductor layer. FIGS. 1 and 2 typically show the CMOS circuit that comprises the complementary combination of the n-channel TFT with the p-channel TFT. However, the present invention can be applied also to an NMOS circuit using the n-channel TFTs, a pixel matrix circuit of a liquid crystal display device, an EL display device, a read circuit of an image sensor, and so forth.

Example 2

In this example, a method of fabricating an active matrix substrate having a pixel matrix circuit and a CMOS circuit as a basic form of a driving circuit disposed around, and formed simultaneously with, the pixel matrix circuit, will be explained with reference to FIGS. 3 to 5. First, a nitrogen-rich silicon nitride oxide film 302a is formed as a first insulating layer on a substrate 301 to a thickness of 50 to 500 nm, typically to a thickness of 100 nm. A silicon nitride oxide film 302b is formed further to a thickness of 100 to 500 nm, typically to a thickness of 200 nm. The nitrogen-rich silicon nitride oxide film 302a has a nitrogen concentration of at least 25 atomic % to less than 50 atomic %. The silicon nitride oxide film 302b is produced from SiH4, N2O and NH3. Island-like crystalline semiconductor films 303, 304 and 305 and a gate insulating film 306 are further formed. The island-like crystalline semiconductor films are obtained by crystallizing an amorphous semiconductor film by using a catalytic element and separating the film into the island form. The gate insulating film 306 is a silicon nitride oxide film produced from SiH4 and N2O and is formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm (FIG. 3(A)).

Next, resist masks 307 to 311 that cover the channel formation regions of the island-like semiconductor films 303, 304 and 305 are formed. At this time, the resist mask 309 may be formed in a region for forming a wiring, too. An n type imparting impurity element is added so as to form impurity regions 312 to 316. Phosphorus (P) is added by ion doping using phosphine (PH3). In this process step, phosphorus is introduced into the island-like semiconductor film below the gate insulating film 306 through this film 306. Therefore, an acceleration voltage is set to 65 keV. The concentration of phosphorus added to the island-like semiconductor is preferably within the range of 1×1016 to 1×1019 atoms/cm3 and is hereby set to 1×1018 atoms/cm3. There are thus formed the P-doped impurity regions 312 to 316. A part of the regions is to serve as the second impurity region that functions as the LDD region (FIG. 3(B)).

Thereafter, the resist mask is removed, and a tantalum nitride (TaN) film 317 and a tantalum (Ta) film 318 are formed by sputtering to a thickness of 10 to 50 nm and 100 to 300 nm, respectively, in order to form a gate electrode. Here, Ta is sputtered using a mixed gas of Ar and Xe (FIG. 3(C)).

Next, resist masks 319 to 324 are formed, and a gate electrode of a p-channel TFT, gate wiring of the CMOS circuit and the pixel matrix circuit and the gate bus line are formed. Unnecessary portions of the TaN film 317 and the Ta film 318 are etched away by dry etching. Etching of the TaN film and Ta film is conducted by using a mixed gas of CF4 and O2. There are thus formed the gate electrode 325 of the p-channel TFT, the gate wiring 327 and the extension wiring 328 and 329. The resist masks 319 to 324 are left as such, and a process step for adding an impurity element for imparting the p type is carried out for a part of the island-like semiconductor films on which the p-channel TFT is formed. Here, boron is selected as the impurity element, and ion doping is conducted using diborane (B2H6). The boron concentration of this region is set to 2×1020 atoms/cm3. There is thus formed the impurity regions 331 and 332 doped with boron in a high concentration as shown in FIG. 4(A).

After the resist masks disposed in FIG. 4(A) are removed, resist masks 333 to 339 are formed afresh. These resist masks are for forming the gate electrodes of the n-channel TFTs, and the gate electrodes 340 to 342 are formed by dry etching. At this time, the gate electrodes 340 to 342 are formed in such a fashion as to overlap with a part of the impurity regions 312 to 316. Holding capacitance electrodes 343 are formed simultaneously in the regions of the semiconductor layer 305 on which the pixel TFTs are formed (FIG. 4(b)).

Next, new resist masks 344 to 350 are formed. The resist masks 345, 348 and 349 are formed in such a shape as to cover the gate electrodes of the n-channel TFTs and a part of the second impurity region, and they determine the offset quantity of the LDD region. A process step is carried out by adding n type imparting impurity element, forming the impurity regions 354 and 355 to serve as the source region and the impurity regions 353, 356 and 357 to serve as the drain region. P-doped impurity regions 351 and 352 are formed at a part of the island-like semiconductor layer 303 in which the p-channel TFTs are to be formed. However, the phosphorus concentration of this region is about ½ of the boron concentration and the conductivity type remains the p type. This process step uses the resist masks 344 to 350, etches away a part of the gate insulating film and exposes the surface of the semiconductor layer to dope the impurity (FIG. 4(C)).

After the process steps up to the step shown in FIG. 4(C) are completed, the first insulating film 358 is constituted by a silicon nitride oxide film by the plasma CVD process using SiH4, N2O and NH3 as the starting materials. This silicon nitride oxide film preferably has a hydrogen concentration of 1 to 30 atomic %. A heat-treatment is then carried out under this state in a nitrogen atmosphere at 400 to 800° C. for 1 to 24 hours, for example, at 525° C., for 8 hours. This process step can activate the n and p type impurities that have been added. The catalytic element that remains in the crystallization step can be segregated into the P-doped regions 351 to 357 as these regions function as the gettering site. As a result, the catalytic element can be removed from at least the channel formation region.

The first hydrogenation step is conducted after this heat-treatment. The hydrogenation step is conducted in a hydrogen atmosphere of 3 to 100% at 300 to 500° C., preferably 350 to 450° C., for 2 to 12 hours. The hydrogenation step may be conducted using hydrogen that is formed by plasma generation, at a substrate temperature of 200 to 500° C., preferably 300 to 450° C. In any case, hydrogen supplied into the first insulating film by this treatment diffuses and a part of this hydrogen can hydrogenate the semiconductor layer (FIG. 5(A)).

The second insulating film 359 is formed by the plasma CVD process using SiH4 and N2O as the starting material at a substrate temperature of 200 to 400° C. After predetermined resist masks are formed, the first and second insulating films 358 and 359 are etched so as to form the contact holes reaching the source and drain regions of the TFT, respectively. The source electrodes 360 and 363 and the drain electrodes 362 and 364 are then formed. An electrode having a three-layered structure of a 100 nm-thick Ti film, a 300 nm-thick Ti-containing Al film and a 150 nm-thick Ti film is used as each of the electrodes, though the electrode is not shown in the drawing.

The third insulating film 365 is then formed from above. The third insulating film may comprise a silicon nitride oxide film formed by the plasma CVD process from SiH4, N2O and NH3 or a silicon nitride film formed from SiH4, N2 and NH3. Prior to the film formation, the second hydrogenation step is conducted by plasma hydrogenation treatment by introducing N2O, N3, NH3 and so forth. Hydrogen that is formed in the gaseous phase by plasma generation is supplied also into the second insulating film. When the substrate is heated in advance to 200 to 400° C., hydrogen can be supplied also to the first insulating film and to the lower layers beneath the first insulating film. The fabrication condition of the third insulating film is not limited, in particular, but the third insulating film is preferably a compact film. Finally, the third hydrogenation step is conducted by heat-treatment in an atmosphere containing hydrogen or nitrogen at 300 to 550° C. for 1 to 12 hours. At this time, hydrogen diffuses from the third insulating film into the second insulating film, from the second insulating film into the first insulating film and then from the first insulating film into the semiconductor layer, and hydrogenation of the semiconductor layer can be accomplished effectively. Hydrogen is emitted from inside the films into the gaseous phase, too, but this emission can be prevented to a certain extent if the third insulating film comprises a compact film, and the loss of hydrogen can be supplemented by supplying hydrogen into the atmosphere.

As a result of the process steps described above, the p-channel TFT is formed in self alignment while the n-channel TFT is formed in non-self alignment. In the n-channel TFT of the CMOS circuit are formed the channel formation region 371, the first impurity regions 373 and 374 and the second impurity regions 372 and 373. Here, a region (GOLD region) 372a overlapping with the gate electrode and a region (LDD region) 372b not overlapping with the gate electrode are formed in the second impurity regions. The first impurity region 373 serves as the source region and the first impurity region 374, as the drain region. In the p-channel TFT are formed the channel formation region 368 and the third impurity regions 369 and 370. The third impurity region 369 serves as the source region and the third impurity region 370, as the drain region. The n-channel TFT of the pixel matrix circuit has a multi-gate structure, and there are formed the channel formation regions 374 and 375, the first impurity regions 377 and 378 and the second impurity region 376. A region 376a overlapping with the gate electrode and a region 376b not overlapping with the gate electrode are formed in the second impurity regions. An impurity element for imparting the n type is doped into the drain side of the n-channel TFT of the pixel matrix circuit in the same concentration as the second impurity region. There are formed the low concentration impurity region 379, the gate insulating film 306 and the holding capacitance electrode 343, and a holding capacitance provided to the pixel matrix circuit is formed simultaneously.

An inter-layer insulating film 366 made of an organic resin is formed to a thickness of about 1,000 nm over the third insulating film. BCB, polyimide, acryl, polyimidamide, or the like, can be used for the organic resin film. The advantages of the use of the organic resin film are that the film formation method is simple and easy, the parasitic capacitance can be reduced because the specific dielectric constant is low, and planarity is high. Organic resin films other than those described above can be used, as well. This example uses the polyimide of the type that can be thermally polymerized after applied to the substrate, and is fired at 300° C. to form the film. Contact holes reaching the drain electrodes 364 are bored in the inter-layer insulating film 366 and pixel electrodes 367 are formed. The pixel electrode 367 uses a transparent conductive film when a transmission type liquid crystal display device is fabricated, and uses a metallic film when a reflection type liquid crystal display device is fabricated. To fabricate the transmission type liquid crystal display device, this example uses an indium tin oxide (ITO) film is formed by sputtering to a thickness of 100 nm. In this way, an active matrix substrate having the CMOS circuit and the pixel matrix circuit formed on the substrate 301 can be produced as shown in FIG. 5(B).

Example 3

This example represents an example with reference to FIG. 6 where an active matrix type liquid crystal display device is fabricated from the active matrix substrate produced in Example 2. First of all, an orientation film 401 is formed on a substrate under the state shown in FIG. 5(B). A polyimide resin is used in most cases for the orientation film of the liquid crystal display device. A transparent conductive film 403 and an orientation film 404 are formed on an opposing substrate 402. After being formed, the orientation film is rubbed so that the liquid crystal molecules are arranged in parallel with a predetermined pre-tilt angle. After these steps, the active matrix substrate having the pixel matrix circuit and the CMOS circuit formed thereon and the opposing substrate are bonded to each other through a sealing material and a spacer (both are not shown) by a known cell assembly process. Thereafter, a liquid crystal material 405 is charged between both substrates and is completely sealed by a sealant (not shown). As a result, the active matrix type liquid crystal display device shown in FIG. 6 can be completed.

Next, the construction of the active matrix type liquid crystal display device of this example will be explained with reference to FIGS. 7 and 8. FIG. 7 is a perspective view of the active matrix substrate of this example. The active matrix substrate comprises a pixel matrix circuit 701, a scanning (gate) line driving circuit 702 and a signal (source) line driving circuit 703 that are formed on a glass substrate 301. Pixel TFTs 700 of the pixel matrix circuit are n-channel TFTs and the driving circuits disposed in the peripheral portions comprise the CMOS circuit as the basic circuit. The scanning (gate) line driving circuit 702 and the signal (source) line driving circuit 703 are connected to the pixel matrix circuit 701 through gate wiring 803 and source wiring 804, respectively.

FIG. 8(A) is a top view of the pixel matrix circuit 701 and covers substantially the top view of one pixel. N-channel TFTs are disposed in the pixel matrix circuit. The gate electrode 803 that is so formed as to continue the gate wiring 803 crosses a semiconductor layer 801 below the gate electrode through a gate insulating film, not shown. The source region, the drain region and the first impurity region are formed in the semiconductor layer, though they are not shown in the drawing. A holding capacitance 807 is constituted by the semiconductor layer, the gate insulating film and the electrode made of the same material as the gate electrode on the drain side of the pixel TFT. The sectional structure along a line A-A′ in FIG. 8 corresponds to the sectional view of the pixel matrix circuit shown in FIG. 6. In the CMOS circuit shown in FIG. 8(B), on the other hand, the gate electrodes 325 and 340 extending from the gate wiring 328 cross the semiconductor layers 303 and 304 below the gate wiring 328 through the gate insulating film, not shown, respectively. Though not shown in the drawing, the source region, the drain region and the LDD region are formed similarly in the semiconductor layer of the n-channel TFT. The source region and the drain region are formed in the semiconductor layer of the p-channel TFT. The sectional structure along a line B-B′ showing the positional relationship corresponds to the sectional view of the pixel matrix circuit shown in FIG. 6.

The pixel TFT of this example has the double-gate structure, but it may be a single gate structure or a multi-gate structure such as a triple-gate structure. The construction of the active matrix substrate of this example is not limited, in particular, to the construction of this example. The feature of the construction of the present invention resides in the construction of the source region and the drain region of the semiconductor layer disposed through the gate insulating film and other impurity regions, and other constructions may be decided appropriately, whenever necessary.

Example 4

This example will be explained with reference to FIGS. 11 to 13. First, a glass substrate such as a Corning #1737 substrate is prepared as a substrate 601. A gate electrode 602 is then formed on the substrate 601. A tantalum (Ta) film is formed to a thickness of 200 nm by sputtering. The gate electrode 602 may have a two-layered structure comprising a tantalum nitride film (thickness of 50 nm) and a Ta film (thickness of 250 nm). The Ta film is formed by sputtering of an Ar gas and Ta as the target. When sputtering is effected using a mixed gas of the Ar gas with a Xe gas, the absolute value of the internal stress can be lowered down to 2×109 dyn/cm2 (FIG. 11(A)).

A gate insulating film 603 and an amorphous semiconductor layer 604 are serially and continuously formed without releasing them to the atmospheric air. The gate insulating film comprises a nitrogen-rich silicon nitride oxide film 603a (thickness of 50 nm) and a silicon nitride oxide film (thickness of 125 nm). The nitrogen-rich silicon nitride oxide film 603a is formed by sputtering by the plasma CVD process that uses a mixed gas of SiH4, N2O and NH3. The amorphous semiconductor layer 604, too, is formed in accordance with the plasma CVD process to a thickness of 20 to 100 nm, preferably 40 to 75 nm (FIG. 11(B)).

Heat-treatment is then carried out at 450 to 550° C. for one hour. This heat-treatment emits hydrogen from the gate insulating film 603 and the amorphous semiconductor layer 604. Thereafter, the crystallization step is applied to the amorphous semiconductor layer 604 to form a crystalline semiconductor layer 605. This crystallization step may use the laser crystallization method or the thermal crystallization method. The laser crystallization method uses a KrF excimer laser beam (wavelength of 248 nm), for example, to form a linear beam. Crystallization of the amorphous semiconductor layer is executed at an oscillation pulse frequency of 30 Hz, a laser energy density of 100 to 500 mJ/cm2 and an overlapping ratio of the linear beams of 96% (FIG. 11(C)).

Next, an insulating film 606 is so formed as to keep contact with the resulting crystalline semiconductor layer 605. Here, a silicon nitride oxide film is formed to a thickness of 200 nm. A resist mask 607 that keeps contact with the insulating film 606 is formed by a patterning process that uses exposure from the back. Here, the gate electrode 602 functions as the mask and the resist mask 607 can be formed in self alignment. The size of the resist mask is a little smaller than the width of the gate electrode due to turn-around of light (FIG. 11(D)). The insulating film 606 is then etched using the resist mask 607 to form a channel protection film 608, and then the resist mask 607 is etched away. This process step exposes the surface of the crystalline semiconductor layer with the exception of the region that keeps contact with the channel protection film 608. The channel protection film 608 plays the role of preventing doping of the impurity into the channel region in a subsequent impurity-doping step (FIG. 11(E)).




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stats Patent Info
Application #
US 20100035424 A1
Publish Date
02/11/2010
Document #
12579020
File Date
10/14/2009
USPTO Class
438585
Other USPTO Classes
438164, 257E2119
International Class
01L21/28
Drawings
22


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