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Method of fabricating a gate structure




Title: Method of fabricating a gate structure.
Abstract: A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure. ...


USPTO Applicaton #: #20090311855
Inventors: Richard A. Bruff, Richard A. Conti, Denise Pendleton-lipinski, Amanda L. Tessier, Brian L. Tessier, Yun-yu Wang, Daewon Yang, Chienfan Yu


The Patent Description & Claims data below is from USPTO Patent Application 20090311855, Method of fabricating a gate structure.




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stats Patent Info
Application #
US 20090311855 A1
Publish Date
12/17/2009
Document #
12544425
File Date
08/20/2009
USPTO Class
438587
Other USPTO Classes
257E2119
International Class
01L21/28
Drawings
4


High Density Liner Mosfet

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Semiconductor Device Manufacturing: Process   Coating With Electrically Or Thermally Conductive Material   Insulated Gate Formation   Forming Array Of Gate Electrodes  

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20091217|20090311855|fabricating a gate structure|A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by |
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