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Method of fabricating a gate structure

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Title: Method of fabricating a gate structure.
Abstract: A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure. ...


USPTO Applicaton #: #20090311855 - Class: 438587 (USPTO) - 12/17/09 - Class 438 
Semiconductor Device Manufacturing: Process > Coating With Electrically Or Thermally Conductive Material >Insulated Gate Formation >Forming Array Of Gate Electrodes

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The Patent Description & Claims data below is from USPTO Patent Application 20090311855, Method of fabricating a gate structure.

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This application is a divisional of U.S. patent application Ser. No. 11/875,222, attorney docket number FIS920070152US1, filed on Oct. 19, 2007, currently pending.

BACKGROUND

1. Technical Field

The disclosure relates to fabrication of a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof. More particularly, the disclosure relates to the fabrication of a gate structure where single-layer or dual-layer nitride liners are used to boost N-channel MOSFET (NFET) and P-channel MOSFET (PFET) performance, respectively.

2. Related Art

In the current state of the art, continued scaling of gate structures in complimentary metal oxide semiconductors (CMOS), use gate-spacer integration and strain engineering by one or more selective thin film deposition to enhance carrier mobility. Typically, plasma enhanced chemical vapor deposition (PECVD) is used to deposit a nitride film or films for forming a single or dual-layer nitride integration to boost NFET and PFET performance. With each film deposited as a single layer having uniform properties, the extent of control over conformality and adequate stress is limited. This limitation and the shape of the spacer having a vertical space extending from between the bases of adjacent gates tend to create voids in gate structures. The voids, which are subsequently filled by metal, result in electrical shorted paths at a contact level. This is particularly severe in the second liner deposition process, and more so in the case of PFET liners, which require compressive plasma enhanced nitride for enhancing carrier mobility.

FIG. 5 illustrates voids 30 formed in the deposition process of fill structure 40 for filing vertical space 25. Fill structure 40 may include barrier films (not shown) or dual-nitride films (not shown). Such typical fabrication processes use a constant film composition having a constant stress for forming the fill structure 40. Fill structure 40 is usually formed from a single PECVD film. When dual-layer nitride films are used for forming fill structure 40, multiple PECVD films are used. Since each layer of PECVD films shares uniform composition and stress properties, conformality variation in fill structure 40 is limited. This in turn compromises the ability for maintaining adequate composite stress.

Efforts to address the problem of void formation include tapering of spacers, replacing PECVD compressive nitride with high density plasma (HDP) chemical vapor deposition (CVD) nitride or alternating between deposition and reactive-ion-etching (RIE). However, these efforts have their limitations. The tapering of spacers may lead to over-etching of some areas because of the variable pitch of isolated and/or nested features. As to the use of HDP CVD nitride, the significant variable thickness with in a nominal 1000 Å across varied device structures poses a problem for RIE of the compressive nitride because of unavoidable over-etching in some areas. Alternating deposition and RIE is impractical because many cycles are required to prevent void formation. Even with the many cycles, avoidance of void formation is dependent on the profile after each cycle, which is very difficult to control in view of the number of cycles. Therefore the problem of void formation remains.

In view of the foregoing, it is desirable to develop an alternative method for depositing nitride films over a gate structure to obviate void formation in vertical space between adjacent gates within the gate structure.

SUMMARY

A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

A first aspect of the disclosure provides a gate structure comprising: a plurality of gates disposed on a substrate; and at least one dual-layer liner disposed on the plurality of gates and filling a vertical space between adjacent gates, the at least one dual-layer liner including an intrinsically stressed protective layer and an intrinsically stressed filling layer, the intrinsic stress of each of the intrinsically stressed protective layer and the intrinsically stressed filling layer being variable, and wherein the at least one dual-layer liner is formed of high density plasma (HDP) films.

A second aspect of the disclosure provides a method of fabricating a gate structure, the method comprising: forming a plurality of gates on a substrate; and depositing at least one dual-layer liner to fill a vertical space between adjacent gates, the at least one dual-layer liner including an intrinsically stressed protective layer and an intrinsically stressed filling layer, the intrinsic stress of each of the intrinsically stressed protective layer and the intrinsically stressed filling layer being variable, and wherein the depositing is a single step deposition of high density plasma (HDP) films.

A third aspect of the disclosure provides a gate structure comprising: a plurality of gates disposed on a substrate; and at least one tri-layer film stack disposed on the plurality of gates and filling a vertical space between adjacent gates, the at least one tri-layer film stack including at least one dual-layer liner and at least a layer selected from a group consisting of: a capping layer and a base layer, wherein the at least one dual-layer liner includes an intrinsically stressed protective layer and an intrinsically stressed filling layer, the intrinsic stress of each of the intrinsically stressed protective layer and the intrinsically stressed filling layer being variable, and wherein the at least one dual-layer liner is formed of high density plasma (HDP) films.

A fourth aspect of the disclosure provides a gate structure comprising: a plurality of gates disposed on a substrate; and at least one quadric-layer film stack disposed on the plurality of gates and filling a vertical space between adjacent gates, the at least one quadric-layer film stack including at least one dual-layer liner, a base layer and a capping layer, wherein the at least one dual-layer liner includes an intrinsically stressed protective layer and an intrinsically stressed filling layer, the intrinsic stress of each of the intrinsically stressed protective layer and the intrinsically stressed filling layer being variable, and wherein the protective layer and filling layer is formed of a high density plasma (HDP) film, and wherein the at least one dual-layer liner is between the base layer and the capping layer, wherein each of the protective layer, filling layer, base layer and capping layer include an intrinsic stress.

The illustrative aspects of the present disclosure are designed to solve the problems herein described and/or other problems not discussed.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which:

FIG. 1 illustrates a cross-sectional view of an embodiment of a gate structure in a MOSFET.

FIG. 2 illustrates a cross-sectional view of another embodiment of a gate structure in a MOSFET.

FIG. 3 illustrates a cross-sectional view of an alternative embodiment of a gate structure in a MOSFET.

FIG. 4 illustrates a cross-sectional view of yet another embodiment of a gate structure in a MOSFET.

FIG. 5 illustrates a cross-sectional view of a prior art gate structure in a MOSFET with a barrier layer disposed over the gate structure.



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stats Patent Info
Application #
US 20090311855 A1
Publish Date
12/17/2009
Document #
12544425
File Date
08/20/2009
USPTO Class
438587
Other USPTO Classes
257E2119
International Class
01L21/28
Drawings
4


High Density
Liner
Mosfet


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