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Method of forming a thin film transistor

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Title: Method of forming a thin film transistor.
Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer. ...


USPTO Applicaton #: #20090302322 - Class: 257 66 (USPTO) - 12/10/09 - Class 257 


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The Patent Description & Claims data below is from USPTO Patent Application 20090302322, Method of forming a thin film transistor.

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stats Patent Info
Application #
US 20090302322 A1
Publish Date
12/10/2009
Document #
File Date
09/30/2014
USPTO Class
Other USPTO Classes
International Class
Drawings



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