Method and system for parallel histogram calculation in a simd and vliw processor   

This application claims priority under 35 U.S.C 119(e) from co-pending U.S. Provisional Application No. 60/385,722 filed on Jun. 3, 2002 by Tibet Mimar entitled “Method for Parallel Histogram Calculation in a SIMD and VLIW Processor”, the subject matter of which is fully incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to the field of processor chips and specifically to the field of single-instruction multiple-data (SIMD) processors. More particularly, the present invention relates to vector Look-Up Table (LUT) and histogram operations in a SIMD processor.

2. Description of the Background Art

Histogram calculation for video and images has typically been performed as a scalar operation. For example, Imaging and Compression Engine (ICE) chip used by Silicon Graphics O2 workstation featured a 8-wide SIMD architecture was used to implement video and image library operations, but histogram was calculated one component at a time, even though ICE has a dual-instruction issue per-clock-cycle for concurrent I/O and ability to process 8 data in parallel. This resulted in the order of N*M clock cycles to calculate the histogram of N data entries with M components, where components are different colors such as Red, Green, Blue, and Alpha (RGBA).

It is also conceivable that image and video data could be partitioned into K groups, and each of these groups could be passed on to a different processor, or to a part of VLIW processor for concurrent calculation. For example, TI\'s TMS320C62X Image/Video Processing Library uses this technique, where this VLIW processor has 8 separate execution units. This code operates on four interleaved histogram bins, which are later summed together. The benchmark according to this library is 1158 cycles for L=512 data entries, or (9/8)*L+512 in general. This result is no better than order of L operations, despite 8-wide parallel VLIW architecture of \'C62X.

Image and video analysis, histogram equalization, auto focus, and other image enhancement algorithms use histogram calculation. If image has multiple components such as RGBA or YUV (luma and two chroma), different histogram bins are used for each component.

Part of the reason histogram has been limited to a scalar operation is that there was no support for its parallel implementation in a SIMD or VLIW processor.

SUMMARY

The present invention uses vector LUT operations to calculate the histogram in parallel for multiple data points, resulting in a speed up by a factor of N in comparison with scalar calculation, where N is the number SIMD elements and LUT units provided.

For histogram calculation, N values of image/video are read, and vector LUT operation is performed on these components as addresses. Vector LUT does not require a separate dedicated memory, but uses part of the N separate data memory modules of the SIMD processor. For a LUT operation, each of the N memory modules are addressed independently using the corresponding input vector-register element value plus a base address as the address for a given SIMD vector slice. The vector LUT output contains the past occurrence-count values for each of these components. These occurrence values are incremented using a single vector add or increment operation, and then stored back to the vector LUT memory again, using the input vector values (the same input vector register into which input values were read) as the vector LUT addresses.

The present invention requires four vector instructions to perform histogram: input data read, vector LUT read, vector increment, and vector store back. This is exactly the same for scalar calculation of histogram, except histogram for N values are calculated simultaneously, thus, the histogram calculation speed up is by a factor of N. For a preferred embodiment of the present invention, the value of N is 32, i.e., 32 LUTs operating in parallel, and this results in a speed up by a factor of approximately 32×.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated and form a part of this specification, illustrated prior art and embodiments of the invention, and together with the description, serve to explain the principles of the invention.

FIG. 1 illustrates the vector LUT operation using N-element vectors. The data memory is part of processor data memory, and is partitioned into N modules. This data memory is used for regular or vector operations as well as vector LUT operations.

FIG. 2 illustrates vector LUT update operation, which writes input vector register elements to addressed elements of vector LUT memory specified by another vector register.

FIG. 3 illustrates the address calculation for each of the N LUT modules. The address is concatenation of global base address, which must be at power-of-two address boundary, and J least-significant data bits of input vector element for a given vector element.

FIG. 4 illustrates reduction of partial histogram results for the case of RGBA input format and for N equals to 32 (32 wide SIMD.) Eight sets of RGBA histogram entries have to be summed together for the overall result. This is accomplished in three steps using three vector add instructions.

FIG. 5 illustrates the preferred embodiment of present invention where MIPS4000 RISC core is connected to vector SIMD processor. These two processors share the data memory.

DETAILED DESCRIPTION

In the following detailed description of the present invention, numerous specific details are set forth in order to provide a through understanding of the present invention. However, it will be obvious to one skilled on the art that the present invention may be practiced without these specific details. In other instances well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

The present invention features a method for providing vector histogram calculation operations in single-instruction multiple-data (SIMD) operations in a computer system that executes on a vector of N elements for each SIMD instruction. The histogram operation is calculated with SIMD parallelism using vector Look-Up Table (LUT) and vector increment operations.

The preferred embodiment performs 32 LUT operations in a processor having 512-bit wide data memory that is organized as 32 modules of on-chip memory, where each memory module is 16-bits wide. Although a data path of 512-bits and 32-vector elements is exemplified herein, the present invention is readily adaptable to other variations with different N values other than 32.

FIG. 1 illustrates the vector LUT operation. Data memory 100 of the SIMD processor that is 32 elements wide is partitioned into 32 separate memory modules, each of which could be independently addressed for vector LUT operation. A vector register 110 that is 32 elements wide is used to generate the input address for the LUT operation, and the output of LUT from 32 data memories are stored into a vector register 120 that is 32 elements wide.

The block to generate Effective-Address (EA) 130 takes the LUT size, base address, and generates effective address to be provided to each data memory module. There is a separate EA generation logic per each vector element. The effective-address is formed as concatenation of low-order J bits of a vector element value and high-order address bits specified by base address 150. The forming of address for each vector element is illustrated in FIG. 3, where LUT size is 2J entries. Alternatively, base address could be added to each elements address, but the preferred embodiment uses concatenation of addresses in order not to require 32 adders for this operation. The only requirement is that the base address is on a boundary such that the addresses could be concatenated.

The LUT size 140 is determined for all the LUTs by the vector instruction as the number of address bits in a LUT. For example, eight is used for a 256 entry LUT. The base address 150 is determined by a register, which specifies the base of LUT in the data memory.

Table 1 shows the vector LUT instructions for the preferred embodiment. Load Vector LUT (LVLUT) vector look-up table instruction takes a source vector register, a RISC data register, and stores the LUT result in a destination vector register. All source and destination vector registers are part of a vector register file. The LUT size is specified as a constant as part of the instruction. RISC data register specifies the LUT base address in data memory. LUTj refers to jth data memory module.

TABLE 1 Vector LUT Instructions for Histogram Calculation. Instruction Description LVLUT. <n> Load N words from LUT into VRd. VRd, VRs(Rn) For element j = 0 to N − 1 do the following: VRdj ← LUTj (EAj) EAj = (Base Address & !1n) ∥ (VRsj & 1n) SVLUT. <n> Store N words into LUT. VRs-1, VRs-2(Rn) For element j = 0 to N − 1 do the following: LUTj (EAj) ← VRs-1j EA = (Base Address & !1n) ∥ (VRs-2j & 1n) VRs-1: Contains data to store. VRs-2: Contain LUT addresses to access. Notation: VRd, VRs-1, VRs-2, and VRc: Vector registers. !: Local Negation ∥: Concatenation 1n: Binary one repeated “n” times. &: Logical AND operation

Store VLUT (SVLUT) instruction is used to write or update the contents of vector LUT. It requires source vector specify the LUT entries to write and the source vector register that contains the data to write. SVLUT uses the structure shown in FIG. 2. The only difference to FIG. 1 is that vector register contents are written into the LUT, i.e., data memories.

The following steps are used for vector histogram calculation: A. Set the LUT base address register to point to the beginning of histogram table to be stored in data memory. B. Initialize the histogram table area in data memory to zeros. Using vector-write operations, with vector preloaded with zeros, speeds up this operation because it writes N elements in one instruction, e.g., 32 16-bit values in one vector store operation. C. Read a vector of N input values into a vector register, and read the corresponding location for these entries using a vector LUT instruction, LVLUT into a vector register VRd. D. Increment the elements of VRd using a vector addition instruction and adding one to all the elements, or using a vector increment instruction that does the same. This step increments the occurrence value for each of the input values that is read from histogram table. E. Store the incremented VRd from the previous step back into the same entries using a vector LUT update instruction SVLUT. This updates the histogram table. F. Repeat steps C through E for all the data points, processing N input data points at each step. When all the data points are processed, then go to step G. G. Perform necessary vector reduction of vector table. For example, if input data is all in intensity values, then sum all 32 values of each LUT entry for calculating the histogram. If input data is in RBGA (Red-Green-Blue-Alpha) components, then sum each group of eight elements together for each LUT entry. Alpha values may be left out of addition depending upon the application.

Reduction of multiple histogram bins is illustrated in FIG. 4 for the case of video with {RGBA} components, i.e., four components per pixel. If there are 32 elements per vector, then this means there are eight RGBA histogram bins per LUT entry. The corresponding four components of these eight bins have to be summed together. This could be done using tree of adders, which could be implemented as three vector addition instructions of SIMD.

Histogram calculations may be done with or without clamping when the total occurrences exceed the maximum LUT output value. For example, typically we would use a 256 entry LUT (i.e., 8-bit address) and where LUT output is 16-bits. In a large image if there are more than 65,536 values, the histogram table entry could overflow and wrap-around, but this is allowed by openGL standard. If this is not allowed then, vector addition with saturation to maximum value has to be used.

The example code fragment to calculate the histogram is shown bellow. This code is the same regardless of the number of vector elements, i.e., the parallelism of the present invention. VR0 to VR31 are the vector registers of the SIMD processor and R0 to R31 are the registers of the RISC processor. LDV is the vector load instruction, VINC is the vector increment instruction, and “//” indicate comment fields.

//R1 → Input Data //R2 → LUT Base Address LDV VR1, (R1); // Read Input vector LVLUT VR2, VR1 (R2); // Perform Vector LUT: R1 ← Past Occurrence Count VINC VR2, VR2; // Increment occurrence counts for all elements SVLUT VR2, VR1 (R2); // Write back updated counts to vector LUT The reduction of multiple histogram bins could be done as a post processing of the whole LUT, or selectively for only the interested histogram entries.

The best way to implement the present invention is using at minimum a dual-issue processor, where during each clock cycle two instructions are issued: One scalar instruction and one vector instruction for SIMD operations, as shown in FIG. 5. SIMD has 32 vector elements, and each element is 16-bits wide. The scalar processor is a RISC type processor, and handles program flow as well as loading and storing of vector register file registers with special vector load and store instructions. The vector processor operates on vector register file. Using dual-port data memory modules will provide vector LUT operations concurrently with vector load and store instructions by the scalar unit. The data memory is shared by RISC and SIMD processors, and is also used for LUT operations. The data memory is internally partitioned into 32 modules. The data memory is dual-ported so that processing and concurrent DMA is supported.