Input cancellation circuit

Abstract: A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein both paths substantially match in resistance. In another embodiment, a differential signal is substantially cancelled by a pseudo differential arrangement including two independent input resistance paths each in parallel with a corresponding negative resistance path, wherein the resistance paths substantially match the input resistance paths. In yet another embodiment, a differential signal is substantially cancelled by a differential arrangement including two resistance paths wherein a first negative resistance path is coupled between the first differential input and the second differential output and the second negative resistance path is coupled between the second input and the first output. In yet another embodiment, a current controlled current source may provide the negative amplification for the negative resistance path. (end of abstract)

Input cancellation circuit description/claims

Brief Patent Description

Full Patent Description

Patent Application Claims

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyrights whatsoever.

BACKGROUND INFORMATION

The present invention relates in general to input cancellation circuits, and more particularly to input cancellation in resistively coupled circuits.

Low noise resistively coupled circuits may need a small input resistor to ensure that the noise contribution of the input resistor does not dominate the overall noise of the system. The system may need to be isolated, for example, for calibration purposes. To isolate the input, a series switch may be used. However, if the series switch resistance is allowed to dominate over the input resistor, it may result in significant distortion during normal operation due to non-linear junction capacitances. If the series switch resistance is made small with respect to the low input resistance, the large physical size of the switch can introduce significant parasitic capacitance and reduce the bandwidth of the input circuits. Furthermore, if the input is allowed to exceed the supply voltage by more than the gate oxide breakdown of the series switch, then when the series switch is isolated, the oxide of the switch may be exposed to damage.

For example, FIG. 1 shows an input cancellation circuit 100 in accordance with prior art. It comprises an input 110 for receiving an input signal from an external source, a series resistance 130 coupled to the input 110, a switch 140 which may be an NFET transistor, coupled to the series resistance 130, and an output 120 coupled to the output of the switch 140. The NFET used as a switch 140 can add substantial distortion during normal operation due to its non-linear junction capacitance. For a given channel length for the NFET 140, the “ON” resistance is a function of the width or size of the NFET 140. Thus, to reduce the “ON” resistance, the width of the NFET 140 needs be increased. However, as the size of the NFET 140 increases, the parasitic capacitance of the device increases with it, thereby reducing the bandwidth of the input circuits. Furthermore, if the input 110 is allowed to exceed the supply voltage by more than the gate oxide breakdown of the NFET 140, then when the NFET 140 is isolated, the oxide of the NFET may be exposed to damage.

Thus, there is a need for a system and method for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is illustrated in the figures of the accompanying drawings, which are meant to be exemplary and not limiting, and in which like references are intended to refer to like or corresponding parts.

FIG. 1 shows an input isolation circuit as may be used in the prior art.

FIG. 2 shows a block diagram of a single ended isolation method in accordance with an embodiment of the invention.

FIG. 3 shows a single ended input isolation circuit with a voltage controlled current source in accordance with an embodiment of the invention.

FIG. 4 shows a diagram of a single ended isolation method in accordance with an embodiment of the invention wherein the negative resistance path includes a resistance and a current controlled current source.

FIG. 5 shows a pseudo-differential input isolation circuit in accordance with an embodiment of the invention.

FIG. 6 shows a differential input isolation circuit in accordance with an embodiment of the invention.

FIG. 7 shows a differential input isolation circuit with a current controlled current source in accordance with an embodiment of the invention.

FIG. 8 shows a switch biasing means in accordance with an embodiment of the invention.

FIG. 9 shows an embodiment of a current controlled current source.

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Industry Class:
Electronic digital logic circuitry

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