Processor apparatus and method of processing multiple data by single instructions

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2008-107061 which was filed on Apr. 16, 2008, and Japanese Patent Application No. 2008-215137 which was filed on Aug. 25, 2008, the disclosure of which is incorporated herein in its entirety by reference.

1. Field of the Invention

The present invention relates to a Single Instruction Multiple Data (SIMD) arithmetic processor, apparatus and a method, an arithmetic processing unit and a compiler used for the SIMD arithmetic processor that obtain a calculation error by a floating-point operation.

2. Description of Related Art

As a high precision operating method using a double precision arithmetic processor, a “double-double” operation is known. The double-double operation is a floating-point type operation that uses two words of double precision type 64 bits. The operation achieves 106 bit accuracy by using two words for high (the MSB side) and low (the LSB side). “MSB” means the “Most Significant Bit”, and “LSB” means the “Least Significant Bit”.

Double-double addition is expressed by a formula below:

(c.hi, c.lo)=(a.hi, a.lo)+(b.hi, b.lo)

a.hi+b.hi=fl (a.hi+b.hi)+err (a.hi+b.hi)=fl.hi+err.hi

a.lo+b.lo=fl (a.lo+b.lo)+err (a.lo+b.lo)=fl.lo+err.lo

A fl (op(A)) means a normalized value of op(A), and an err (op(A)) means a computing error of op(A)).

In order to execute the double-double addition, a roundoff error of the double precision addition result is calculated. For calculating the roundoff error, Dekker\'s algorithm and Knuth\'s algorithm are known.

Knuth\'s algorithm includes six instructions below.

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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

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