Circuit wiring layout in semiconductor memory device and layout method

This application is a divisional of U.S. application Ser. No. 11/259,401 filed on Oct. 26, 2005, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2004-0089600, filed on Nov. 5, 2004, the disclosures of which are herein incorporated by reference herein in their entirety.

The present invention relates to a semiconductor memory, and more particularly, to a circuit layout in a SRAM semiconductor memory device.

Very large scale integration, (VLSI), has allowed the electronics industry to reduce cost while continuing to increase chip performance and chip reliability. The performance of SRAM (Static Random Access Memory) chips may also be increased by reducing the device dimensions.

Volatile semiconductor memory devices such as SRAMs are achieving higher speed and integration (miniaturization), corresponding to a growing demand for higher performance electronic systems such as personal computers or electronic communication equipments (e.g., cell phones, PDAs, etc.). Manufacturers of memory chips are making great efforts to improve the layout and manufacture of memory cells and peripheral circuits (which select and read the memory cells, such as sense amplifiers) connected with the memory cells, by reducing their dimensions. A circuit wiring layout technique in a peripheral circuit region has an important impact on the integration (miniaturization) level, the peripheral circuit region being adjacent to a memory cell (array) region where the size of memory cells is reduced by advanced process techniques.

FIG. 1 is a block diagram illustrating a semiconductor memory device including its memory cell array and its peripheral circuit blocks. Referring to FIG. 1, the device includes a memory cell array 110 having a plurality of memory cell blocks each constructed of a plurality of memory cells; an X decoder 130 for selecting a row of memory cells; a Y decoder 140 for selecting a column of memory cells (disposed in the memory cell array 110); a column (Y) gating block 120 connected to the Y decoder 140, to designate a column (Y) path of the memory cell array 110; a block write driver 150 connected to the column (Y) gating block 120, to provide write data to a memory cell; and a block sense amplifier (S/A) 160 connected to the column (Y) gating block 120, to sense and amplify (read) data stored in a memory cell.

FIG. 2 is a circuit diagram of a representative portion of the column (Y) gating block 120 shown in FIG. 1. FIG. 2 shows, for illustrative convenience, a pair of circuit wiring structures connected with two mutually adjacent memory cells 1a and 1b (within the memory cell array 110). Referring to FIG. 2, a precharge and equalization part 122a and a read and write path switching part 124a are connected to a first bit line pair BL0, BL0B of the first memory cell 1a. A second bit line pair BL1, BL1B (of the second memory cell 1b) is connected with a similar precharge and equalization part 122b and a read and write path switching part 124b.

A pair of P-type FET (e.g., MOS; MOSFET Metal Oxide Semiconductor Field Effect Transistor) transistors Tp00 and Tp01 (in the precharge and equalization part 122a) precharge the first bit line pair BL0, BL0B to a power source voltage VDD, and a P-type MOS equalizing transistor Te0 maintains the paired bit lines BL0 and BL0B at the same voltage potential during an equalization operation. Similarly, a second pair of P-type MOS transistors Tp10 and Tp11 (in the precharge and equalization part 122b) are precharge transistors for precharging the bit line pair BL1, BL1B to the power source voltage VDD, and a P-type MOS transistor Te1 is an equalizing transistor for maintaining the second pair of bit lines BL1 and BL1B at the same potential (relative to each other) during an equalization operation.

In the read and write path switching part 124a, P-type MOS transistors Tr0 and Tr0B are turned ON for a read operation, to transfer potentials appearing on the bit line pair BL0, BL0B to a read related circuit such as a sense amplifier etc.; and N-type MOS transistors Tw0, Tw0B are turned ON during a write operation, to transfer an applied write data to the bit line pair BL0, BL0B.

Similarly, in the read and write path switching part 124b, P-type MOS transistors Tr1 and Tr1B are read path switching transistors that are turned ON during a read operation to transfer potentials appearing on the bit line pair BL1, BL1B to a read related circuit such as a sense amplifier etc.; and N-type MOS transistors Tw1, Tw1B are write path switching transistors that are turned ON during a write operation to transfer an applied write data to the bit line pair BL1, BL1B.

FIG. 3 is a circuit diagram of a conventional six-transistor SRAM (static random access memory) cell for implementing the volatile memory cells shown in FIG. 2.

The circuit structure for each of the memory cells 1a and 1b shown in FIG. 2 may be a conventional CMOS (Complementary Metal Oxide Semiconductor) SRAM (Static Random Access Memory) cell constructed of six transistors M1-M4, P1 and P2, as shown in FIG. 3. If the cell pitch of SRAM cell is reduced down to the approximate resolution limit of a photolithography process, the six transistors may be disposed on mutually different layers instead of a disposition on the same layer.

Regardless of the disposition of transistors constituting the memory cell on the same layer or mutually different layers, when the cell pitch of a memory cell is reduced, it is more difficult to form similarly sized transistors constituting the precharge and equalization part and the read and write path switching part. It is difficult to form the P-type and N-type transistors shown in FIG. 2, matching the pitch size of a minimal pitch memory cell.

Further, signal lines of column decoding signals Y0 and Y1 among signal lines of column decoding signals Y0, Y0B, Y1 and Y1B of FIG. 2 must be respectively connected with connection nodes co1 and co2 of FIG. 2, thus the line loading is large. Since parasitic resistances PR1, PR2, PR11 and PR22 may have very large values, errors in write operation may occur.

Meanwhile, a row decoder section 130a in being a portion of) the X decoder 130 of FIG. 1 may have a circuit wiring structure as illustrated in FIG. 8. The row decoder section 130a (FIG. 8) formed in a functional circuit region near a memory cell region can be constructed of four (inverting) drivers in a case where four subword lines SWL0-SWL3 are connected to one corresponding main word line MWL 100. If the cell pitch of memory cells connected to the subword lines SWL0-SWL3 is minimized, it is very important to form input lines 60, 61, 62 and 63 of the drivers. Each of input lines 60, 61, 62 and 63 individually transmits a block selection (BLK-SEL) signal SiDi corresponding to a selection signal to a respective one of the subword lines SWL0-SWL3 of FIG. 8. In other words, it is very difficult to form P-type transistors 10-13 and N-type transistors 20-23 (constituting the drivers and their input/output wires) that match a minimized memory cell pitch.

FIGS. 4A and 4B are plan views of a conventional layout of the conventional circuit of FIG. 2. Memory cells 1a and 1b of FIG. 4A respectively correspond to memory cells 1a and 1b of FIG. 2, and equalization transistors Te0 and Te1 are formed (elongated) in a Y direction in a region S10 (for convenience, an X direction is called a first direction and a Y direction is called a second direction). The reference number 2 (e.g., in the region S10) indicates a P-type (semiconductor) active region formed in or on a (semiconductor) substrate, and a reference symbol WC of the rectangular elements indicates that they are tungsten contacts. An “active region” means an area within which transistors or other active devices reside. The tungsten contacts WC electrically connect metal layers (corresponding to drain and source regions of the equalization transistors Te0 and Te1) to the Bit line pairs BL0-BL0B and BL1-BL1B, respectively.

Bit line pairs BL0-BL0B and BL1-BL1B shown in FIGS. 4A & 4B are depicted by dotted lines (rectangles extending in the second (Y) direction). Each gate (layer) is formed of a layer of polysilicon, which is often called a “gate poly” by those skilled in the art, and is depicted by a solid perimeter line (hatched in a diagonal pattern) along (a rectangle elongated in the second (Y) direction in the region S10). For convenience, reference characters indicating the equalization transistors Te0 and Te1 are labeled on the gates (e.g., poly (GP) layer) of the equalization transistors Te0 and Te1, in FIG. 4A.

A transistor gate electrode (e.g., a polysilicon gate electrode) is an electrode that regulates the flow of current in a MOSFET (MOS) transistor. The gate electrode of a MOSFET controls the flow of electrical current through the channel between the source and the drain. A thin, high-quality silicon dioxide film called a gate oxide separates the (poly) gate electrode of a MOS transistor from the electrically conducting transistor channel.

The precharge transistors Tp00, Tp01, Tp10 and Tp11 of FIG. 2 are disposed in a region S11 shown in FIG. 4A, and in regions S12 and S13 of FIG. 4B. Write path switching transistors Tw0 and Tw1 and write path switching transistors Tw0B and Tw1B are respectively disposed in regions S12 and S13 of FIG. 4B. In general, the write path switching transistors Tw0, Tw1, Tw0B and Tw1B are disposed within N-type semiconductor active regions, denoted by numeral 4.

Further, read path switching transistors Tr0 and Tr1 and read path switching transistors Tr0B and Tr1B are respectively disposed in P-type active regions, denoted by numeral 2 in regions S14 and S15 of FIG. 4B.