10gbase-t training algorithm

This application is cross-referenced to and claims the benefit from U.S. Provisional Patent Application 60/900180 filed Feb. 7, 2007, which is hereby incorporated by reference.

The invention relates generally to electronic communication systems. More particularly, the invention relates to a training pattern to enable recognition of proper wire-pair orientation and correction in electronic communication systems.

In Ethernet 10GBase-T cabling, the data is sent over four pairs of wires. Between the transmitter and receiver, the pairs can be swapped with each other, and the wires in a pair can be swapped. These reconfigurations can result in an inverted signal or the latency of the four pairs can differ. 10GBASE-T, or IEEE 802.3an-2006, is a standard to provide 10 gigabit/second connections over conventional unshielded or shielded twisted pair cables, over distances up to 100 m. This standard mandates specific training patterns to enable recognition of the proper correction, but does not provide a means to find the proper corrections from all the possibilities. Accordingly, there is a need to develop an algorithm to efficiently search the possible corrections and identify the correct one.

The current invention is a method of recognizing inverted signals and latency difference in wire pairs between a transmitter and receiver in 10GBase-T Ethernet cabling due to wire pair mismatch, and correcting the inversion and latency by swapping the cable orders. The method includes providing four pairs of wires, wherein the wires transmit data between the transmitter and the receiver. The wire pairs include pairs A,B, C, and D, whereas the pairs are arranged in a quadrille pattern having two top pairs and two bottom pairs. The method includes providing a pair swapping state machine, where the swapping state machine selects one pair from the top pairs, whereas the selected pair is designated as pair A. A polarity swapping and scrambler lock state machine is provided, where the lock state machine determines if the designated pair A is a correct choice for position A. The lock state machine then determines if the selected pair is inverted. If the selection for A is not correct a next pair of the wires is designated as pair A and the determination is repeated until the requirements for pair A are met and the pair is not inverted. A slave tap state machine is provided, where the tap state machine establishes a rule for a correct B, C, and D pattern based on the determined pair A. The lock state machine is used to designate a second top pair as pair B. The lock state machine is further used to designate a first bottom pair as pair C and to designate a first bottom pair as pair D. A deskew state machine is provided, where the deskew state machine compares all the designations over all possible latencies with the rules generated by the slave tap machine, where if the rules are not satisfied, the cable swap state machine reverses the designated pair C with designated pair D. The deskew state machine is used to re-compare all the designations over all possible latencies with the rules generated by the slave tap machine, where if the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.

Details of various embodiments of the present invention are disclosed in the following appendices:

• Appendix A.
• Appendix B.
• Appendix C.

As one of ordinary skill in the art will appreciate, various changes, substitutions, and alterations could be made or otherwise implemented without departing from the principles of the present invention. Accordingly, the examples and drawings disclosed herein including the appendix are for purposes of illustrating the preferred embodiments of the present invention and are not to be construed as limiting the invention.