Programmable array logic circuit employing non-volatile ferromagnetic memory cells

This application is a continuation of co-pending U.S. application Ser. No. 11/889,908, which was filed Aug. 17, 2007, and is allowed, which is a continuation of U.S. application Ser. No. 11/580,064, which was filed Oct. 13, 2006 and issued as U.S. Pat. No. 7,285,983, which is a continuation of U.S. application Ser. No. 11/037,696, which was filed on Jan. 18, 2005 and issued as U.S. Pat. No. 7,123,050, which is a divisional of U.S. application Ser. No. 10/239,133, which was filed Jan. 20, 2001 and issued as U.S. Pat. No. 6,864,711, which was a U.S. national phase of International Application Number PCT/US01/01793, which was filed Jan. 20, 2001, which claims the benefit of No. 60/177,533 filed Jan. 21, 2000.

1. The Field of the Invention

The present invention relates generally to a programmable array logic circuit employing non-volatile ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data.

2. The Background Art

Programmable logic devices have any number product sets, usually in groups of four (4), eight (8), sixteen (16) or more bits, although of ten in groups often (10). The arrays are programmed for application-specific tasks to be performed within digital electronic circuits. The fusible link types cannot be re-programmed, but those employing EEPROM and Flash can. For those PALs which use fusible links, the data in the “D” registers is lost at power off. For those that use EEPROM and Flash as replacements for the “D” registers, data is not lost at power off time.

Up to the present, traditional PALs have used “D” type flip-flops for product registers. Lately, however, some fabricators have begun using EEPROM and Flash technology to replace these. These last two technologies have draw-backs, however. EEPROMs are cumbersome to re-program, both are slow to re-program, exhibit “write fatigue,” thereby limiting their useful life, and must be mass-written to re-program.

It has been recognized that it would be advantageous to develop a programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells.

It is an advantage of the invention to have the ferromagnetic memory cells or bits to store data even when there is no power provided to the circuitry. Thus, saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down.

Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein.

The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal, and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line.

Additionally, the integrated circuit may further include a logical AND array and a logical OR array.

Additional features and advantages of the invention will be set forth in the detailed description which follows, taken in conjunction with the accompanying drawing, which together illustrate by way of example, the features of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of a preferred embodiment of the present invention.

FIG. 2 is a schematic of a preferred embodiment of the present invention.

FIG. 3 is a cross sectional view of a single ferromagnetic memory bit.

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Semiconductor memory device
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Programmable device, electronic device, and method for controlling programmable device
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