Pseudo-random bit sequence (prbs) synchronization for interconnects with dual-tap scrambling devices

This application is a continuation application of U.S. patent application Ser. No. 12/098,878, filed Apr. 7, 2008, which is hereby incorporated by reference.

The present teachings relate to devices and methods for pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling.

In wire-based communication systems, information additional to the system data is typically queued up and transmitted in series with the system data as bandwidth permits. One problem of particular concern to communication systems having data rates in the Gbit/s range is that the printed wires of a printed circuit board (PCB) backplane or the lossy transmission lines of a ceramic multi-chip carrier introduces large amounts of unwanted intersymbol interference (ISI) in the data transmission system.

One conventional method employed to reduce ISI introduced timing jitter is based on coding or scrambling of the data stream to guarantee that no long run lengths occur. Specifically, data scrambling, such as, for example, with pseudo-random bit sequences (PRBS) may be used in high-speed interconnects such as, for example, processor-memory links to improve performance by reducing ISI. In communication systems, a scrambler is defined as a device that manipulates by “randomizing” a data stream before transmitting. The manipulations are reversed by a descrambler, which removes the randomization, at the receiving side. Scrambling techniques are widely used in satellite, radio relay communications, high-speed board-to-board and chip-to-chip communication, such as in processor-memory systems.

One conventional scrambler, as shown in FIG. 1, is an additive scrambler, which transforms an input data stream by applying a PRBS by modulo-two adder, also known as an exclusive OR (XOR) gate. Typically, a simple conventional PRBS generator may be implemented electronically by a linear feedback shift register (LFSR). Sometimes a pre-calculated PRBS stored in memory is used to generate the PRBS, but more often the PRBS is generated by an LFSR.

In an LFSR, the feedback function is simply the XOR of certain bits in the register, which are referred to as “taps”. As the bits shift within the register, the list of bits\' positions that affect the next state is called the “tap sequence.” In other words, the taps are the outputs that influence the input.

The tap sequence of an LFSR can be represented as a feedback polynomial or characteristic polynomial. For example, FIG. 1 is a 14-bit LFSR tapped at the 14^th, 13^th, 12^th, 2^nd and 1^st bits and the corresponding polynomial is:

x¹⁴+x¹³+x¹²+x²+1.

The powers of the terms represent the tapped bits, counting from the left. The first and last bits are always connected as an input and tap, respectively. In the diagram of FIG. 1, the tap sequence is [14, 13, 12, 2, 0], where the 0 corresponds to the x⁰=1^st bit. The taps are XOR\'d sequentially with the output and then feed back into the leftmost bit.

Conventional additive scramblers, as discussed above, are commonly referred to as synchronous. In order to assure a synchronous operation of the transmitting and receiving LFSR, a sync word is typically used.

In computing, a sync word is used to synchronize data. For example, when a receiver is receiving a bit stream of data, it needs to know where the header information starts. A predefined sync word is used to indicate the start of data. The sync word is a pattern that is placed in the data stream through equal intervals (that is, in each frame). A receiver searches for a few sync words in adjacent frames and hence determines the place when its LFSR must be reloaded with a pre-defined initial state or value, called the “seed”, which is used to set the initial state of the generator.

If the LFSR is initialized with an initial seed value, it will produce a sequence of internal states before repeating. Because the operation of the register is deterministic, the sequence of values produced by the register is completely determined by its current (or previous) state. Because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle.

In parallel-lane configurations, such as bus-like interconnects, typically, it is beneficial to employ time-shifted maximum-length PRBS sequences for the scrambling of each lane. The first number of the polynomial is the length of the LFSR. The period of a shift register is the length of the output sequence before it starts repeating. Many examples of tables of primitive polynomials from which maximal LFSRs can be constructed can be found in numerous references, which is beyond this discussion.

One benefit of employing time-shifted maximum length PRBS sequences is that this configuration avoids lane-to-lane correlation and minimizes cross-talk. In such a configuration, the time shifts should exceed the expected maximum lane-to-lane skew which may be fairly large in applications such as fully-buffered dual in-line memory module (FB-DIMM: 46 UI; FB-DIMM successors: ˜90 Unit Interval (UI)). Time-shifted PRBS sequences are simply produced by an XOR function of two LFSR taps, as described above. The binomial order of the PRBS sequence should be large enough to allow the selection of the tap pairs for a given number of lanes with the required phase separation. Furthermore, selection of the taps should minimize the LFSR load imbalance.

Scrambling with PRBS sequences requires synchronization of the generator LFSRs in the transmitter (TX) with the analyzer LFSR in the receiver (RX) during the system\'s startup or training sequence. In conventional devices, this is usually achieved by seeding of the RX LFSR with the PRBS sequence from the TX, but this only works in conventional devices if the sequence is produced by a single tap. Therefore, one conventional solution is to scramble the data of one lane (hereinafter referred to as “lane XX”) with the PRBS sequence from a single LFSR tap, while all other lanes use tap-pair sequences. Such a configuration allows the LFSR seeding technique to be applied on lane XX, as shown in FIG. 2. Another conventional solution is to externally send a synchronization control signal to both the transmitter and to the receiver that initiates a parallel load operation of the PRBS LFSRs with a fixed starting pattern. A mechanism to adapt the delay of this control signal to the data delay needs to be provided at high transmission speeds. Yet another conventional, but rather complex solution that would also allow dual tap scrambling is to transmit part of the synchronization and delay information from a TX controller on the data lanes unscrambled, so that a controller in the RX can parallel load a predetermined pattern into the RX LFSR in sync with the TX, as depicted in FIG. 3.

Therefore, it may be desirable to provide a synchronization device and apparatus that allow synchronization of the RX PRBS analyzer with the TX PRBS generator in situations where all lanes are scrambled with dual-tap sequences, and the transmission of unscrambled information across the link is not permitted. It may also be desirable to provide time shifts that exceed the expected maximum lane-to-lane skew, even for fairly large applications. It may further be desirable to provide a binomial order of the PRBS sequence that is large enough to allow the selection of the tap pairs for a given number of lanes satisfying the required phase separation. It may also be desirable to provide a device and method capable of selecting taps that minimizes a communication\'s system LFSR load imbalance.

The present invention may satisfy one or more of the above-mentioned desirable features. Other features and/or aspects may become apparent from the description which follows.

A system for synchronizing interconnects in a link system according to various embodiment can include a computer configured to receive input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scramble the input data at the transmit side, via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmit the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler, and the receive side directly connected to the transmit side via the bus; perform synchronization of the at least one pseudo-random bit sequence scrambler with the at east one pseudo-random bit sequence descrambler. The synchronization transmits from the transmit side to the receive side a synchronization notification via an out-of-band communication; transmits from the transmit side all zero bits to the receive side; loads a scrambling pattern into the at least one pseudo-random bit sequence scrambler and transmits the scrambled data from the transmit side to the receive side; detects a state transition within the transmitted scrambled data employing an edge detection device positioned at the receive side of one of the plurality of lanes used as a synchronization lane; loads and initiate within the at least one pseudo-random bit sequence descrambler a predetermined descrambling pattern. The computer is further configured to de-scramble the transmitted scrambled data at the receive side resulting in the input data; after completing the synchronization, perform a skew correction on the synchronization lane by adjusting at least one FIFO pointer on the synchronization lane; and after skew correction on the synchronization lane, perform a skew correction on any remaining skewed lanes of the plurality of lanes by adjusting at least one FIFO pointer on each of the skewed lanes.