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Fabrication method and structure for providing a recessed channel in a nonvolatile memory device / Samsung Electronics Co., Ltd.




Title: Fabrication method and structure for providing a recessed channel in a nonvolatile memory device.
Abstract: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate. ...


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USPTO Applicaton #: #20090200596
Inventors: Sang-pil Sim, Kwang-soo Kim, Chan-kwang Park, Heon-kyu Lee


The Patent Description & Claims data below is from USPTO Patent Application 20090200596, Fabrication method and structure for providing a recessed channel in a nonvolatile memory device.

CROSS-REFERENCE TO RELATED APPLICATIONS

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This is a divisional of U.S. non-provisional application Ser. No. 11/583,796, filed Oct. 20, 2006, which is incorporated herein by reference in its entirety.

BACKGROUND

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OF THE INVENTION

1. Field of the Invention

The present disclosure relates to manufacturing methods for semiconductor memory devices and, more particularly, to fabrication methods and structures for providing recessed channels in nonvolatile memory devices.

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2005-103866 filed on Nov. 1, 2005, and Korean Patent Application No. 2006-55061 filed on Jun. 19, 2006, the entire contents of which are hereby incorporated by reference.

2. Description of Related Art

With higher integration of semiconductor devices, various physical limitations may affect the performance of the semiconductor devices. For example, because of high integration densities, a channel length of the device may become shorter. The shorter channel length of the device may lead to problems such as, for example, a punch-through effect. In order to overcome such limitations associated with the channel length of the semiconductor device, various structures and fabrication methods for extending a channel length in a highly integrated semiconductor device have been studied.

One such example of a highly integrated semiconductor device includes a recessed channel array transistor (RCAT). The structure of the RCAT includes sidewalls and a recessed region. Specifically, the bottom of the recessed region is used for a channel region.

A conventional method for fabricating a nonvolatile memory device having the recessed channels is as follows. A device isolation layer is formed in a semiconductor substrate. This device isolation layer may be used to define an active region. Furthermore, the defined active region may include the channel for the semiconductor device. Specifically, the recessed region for the channel is formed in the active region. In addition, the recessed region may have a width smaller than that of the active region. Thus, it may be beneficial to form a photoresist pattern having an opening that is smaller than the dimensions of the active region. In particular, the opening of the photoresist pattern defines the recessed region.

While the disclosed RCAT provides for higher integration densities in semiconductor devices, it suffers from several shortcomings. For example, with higher integration of semiconductor devices, it may become more difficult to precisely arrange the photoresist pattern having a smaller opening.

In addition, the higher integration of nonvolatile semiconductor devices also leads to narrower widths of floating gates. The narrow widths of floating gates may also cause many problems. For example, the narrow floating gates may have insufficient processing margins because of the gates' reduced width. This reduction in processing margins may make it difficult to compensate for the misalignment that occurs when patterning the floating gates. In order to solve this problem, the floating gates may be arranged in self-alignment with the device isolation layer. In this case, the device isolation layer is designed to have a height corresponding to a height of the floating gates. However, it may be practically very difficult to implement such a precise photoresist pattern for the recessed regions in the structure of the device isolation layer having a high surface. This is because the depth of focus (DOF) margin becomes smaller because of such a physical limitation.

The present disclosure is directed towards overcoming one or more problems associated with the prior art semiconductor devices.

SUMMARY

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OF THE INVENTION

One aspect of the present disclosure includes a method of fabricating a nonvolatile memory device. The method includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. In addition, the method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method also includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method also includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region. The method also includes forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

Another aspect of the present disclosure includes a method of fabricating a nonvolatile memory device. The method includes preparing a semiconductor substrate including a cell array region. The method also includes forming a pad oxide layer and a first hard mask layer on the semiconductor substrate. The method also includes forming first hard mask patterns and pad oxide patterns by patterning the first hard mask layer and the pad oxide layer in the cell array region, the first hard mask patterns being formed in parallel with each other and crossing over the semiconductor substrate, and the pad oxide patterns being formed under the first hard mask patterns. In addition, the method includes forming pluralities of recessed regions in the semiconductor substrate by patterning the semiconductor substrate by using the first hard mask patterns as an etch mask. The method also includes exposing the pad oxide patterns by removing the first hard mask patterns. The method also includes forming pluralities of second hard mask patterns such that the pluralities of second hard mask patterns are parallel with each other and intersect the recessed regions on the semiconductor substrate where the pad oxide patterns are exposed. The method also includes etching the pad oxide patterns and the semiconductor substrate to form a first trench, and etching the semiconductor substrate at the bottoms of the recessed regions to form a second trench deeper than the first trench, by using the second hard mask patterns as an etch mask. The method also includes forming a device isolation layer having rugged bottoms and defining an action region by filling an insulating material in the first and second trenches. The method also includes exposing the semiconductor substrate including the recessed regions adjacent to the device isolation layer by removing the second hard mask patterns and the pad oxide patterns. In addition the method includes forming a gate insulation layer on the exposed semiconductor substrate. The method also includes forming gate structures on the gate insulation layer to fill the recessed regions, each of the gate structures including a floating gate, an interlevel gate insulation pattern, and a control gate.

Another aspect of the present disclosure includes a nonvolatile memory device. The nonvolatile memory device includes a semiconductor substrate including a cell array region. The memory device also includes a device isolation layer having a rugged bottom profile with shallower and deeper bottoms, intersecting the semiconductor substrate in the cell array region and defining an active region, wherein the active region comprises a recessed region. The memory device also includes a gate insulation layer on the active region. The memory device also includes a gate structure including a control gate, an intergate insulating layer, and a floating gate on the gate insulation layer, wherein the gate insulation layer is conformably provided along a profile of the recessed region and the floating gate is provided to fill the recessed region.

Yet another aspect of the present disclosure includes a nonvolatile memory device. The memory device includes device isolation layers provided in parallel with each other in a semiconductor substrate, defining active regions. The memory device also includes pluralities of parallel word lines intersecting the device isolation layers on the semiconductor substrate. The memory device also includes a floating gate interposed between the word lines and the active regions, an intergate insulating pattern interposed between the word lines and the floating gate, a gate insulation layer interposed between the floating gate and the active regions, drain regions provided in the active regions at a first side of the word lines, the drain regions being isolated from each other through the device isolation layers, a common source line provided by connecting the active regions with each other at the second side of the word lines, being parallel with the word lines, a bit line conductively connected to the drain regions, crossing over the word lines, wherein the active region under the floating gate comprises a recessed region, wherein the gate insulation layer is conformably provided along a profile of the recessed region and the floating gate is provided to fill the recessed region, and wherein the device isolation layer has a rugged bottom profile, with shallower and deeper bottoms, along the bit line.

Yet another aspect of the present disclosure includes a nonvolatile memory device. The device includes a semiconductor substrate. The device also includes a device isolation layers formed in parallel with each other in the semiconductor substrate, defining an active region, string and ground selection lines in parallel with each other, crossing over the active region, pluralities of parallel word lines interposed between the string and ground selection lines, crossing over the active region, a first floating gate interposed between the word lines and the active region, a first intergate insulating pattern interposed between the word lines and the first floating gate, a first gate insulation layer interposed between the first floating gate and the active region, a second gate insulation layer interposed between the first floating gate and the active region, a bit line conductively connected to the active region adjacent to the selection lines, intersecting the selection lines, wherein the active region under the selection lines comprises a recessed region, wherein the second gate insulation layer is conformably provided along a profile of the recessed region, and wherein the device isolation layers have a rugged bottom profile with shallower and deeper bottoms along the bit line.

BRIEF DESCRIPTION OF THE FIGURES

The accompanying figures are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain principles of the present disclosure. In the figures:

FIGS. 1 through 11 are perspective views illustrating sequential processing steps of fabricating a NOR-type nonvolatile memory device in accordance with an exemplary disclosed embodiment of the invention;

FIG. 12 is a sectional view taken along line I-I′ of FIG. 11;

FIG. 13 is a plane view illustrating the NOR-type nonvolatile memory device in accordance with an exemplary disclosed embodiment of the invention;

FIG. 14A is a plane view illustrating a NOR-type nonvolatile memory device in accordance with another exemplary disclosed embodiment of the invention;

FIG. 14B is a sectional view taken along line II-II′ of FIG. 14A;

FIG. 15A is a plane view illustrating a NOR-type nonvolatile memory device in accordance with yet another exemplary disclosed embodiment of the invention;

FIG. 15B is a sectional view taken along line III-III′ of FIG. 15A;

FIGS. 16A, 17A, 18A, 19A, 20A, 21A, and 22A are plane views illustrating sequential processing steps of fabricating a NAND-type nonvolatile memory device in accordance with another exemplary disclosed embodiment of the invention;

FIGS. 16B, 17B, 18B, 19B, 20B, 21B, and 22B are sectional views taken along line IV-IV′ of FIGS. 16A, 17A, 18A, 19A, 20A, 21A, and 22A, respectively; and

FIGS. 16C, 17C, 18C, 19C, 20C, 21C, and 22C are sectional views taken along line V-V′ of FIGS. 16A, 17A, 18A, 19A, 20A, 21A, and 22A, respectively.




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stats Patent Info
Application #
US 20090200596 A1
Publish Date
08/13/2009
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
/
Drawings
0




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Samsung Electronics Co., Ltd.


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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)   Field Effect Device   Having Insulated Electrode (e.g., Mosfet, Mos Diode)   Variable Threshold (e.g., Floating Gate Memory Device)   With Floating Gate Electrode   With Additional Contacted Control Electrode  

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20090813|20090200596|fabrication method and structure for providing a recessed channel in a nonvolatile memory device|A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially |Samsung-Electronics-Co-Ltd
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