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The Patent Description data below is from USPTO Patent Application 20090184734 , Method of producing and operating a low power junction field effect transistor
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is a continuation of U.S. patent application Ser. No. 11/635,004, filed Dec. 7, 2006, which claims priority under 35 U.S.C. §119 to U.S. Provisional Application No. 60/748,089, filed Dec. 7, 2005, the entire contents of which are hereby incorporated by reference in their entirety.
TECHNICAL FIELD OF THE INVENTION
Integrated circuits and devices, and methods of producing and/or using such, are disclosed, such as MOS transistors and Junction Field Effect Transistors (JFETs) and circuits.
BACKGROUND OF THE INVENTION
Very Large Scale Integrated Circuits are being scaled to smaller dimensions to gain greater packing density and faster speed in a continuation of the trend of the past thirty years. Currently, CMOS technology is being manufactured with sub-100 nanometer (nm) minimum dimensions in 2005. Scaling CMOS with the minimum line width below 100 nm presents numerous problems to designers of integrated circuits. A few of the problems of the scaled CMOS transistors below 100 nm are highlighted below;
SUMMARY OF THE INVENTION
The prior art in junction field effect transistors dates back to the 1950s when they were first reported. Since then, they have been covered in numerous texts such as “Physics of Semiconductor Devices” by Simon Sze and “Physics and Technology of Semiconductor Devices” by Andy Grove. Junction field effect devices were reported in both elemental and compound semiconductors. Numerous circuits with junction field effect transistors have been reported, as follows; such as:
DETAILED DESCRIPTION OF THE INVENTION
Nanver and Goudena, “Design considerations for Integrated High-Frequency p-Channel JFET's”, IEEE Transactions Electron Devices, vol. 35, No. 11, 1988, pp. 1924-1933.
O. Ozawa, “Electrical Properties of a Triode Like Silicon Vertical Channel JFET”, IEEE Transcations Electron Devices vol. ED-27, No. 11, 1980, pp. 2115-2123.
H. Takanagi and G. Kano, “Complementary JFET Negative-Resistance Devices”, IEEE Journal of Solid State Circuits, vol. SC-10, No. 6, December 1975, pp. 509-515.
A. Hamade and J. Albarran, “A JFET/Bipolar Eight-Channel Analog Multiplexer”. IEEE Journal of Solid State Circuits, vol. SC-16, No. 6, December 1978.
K. Lehovec and R. Zuleeg, “Analysis of GaAs FET's for Integrated Logic”, IEEE Transaction on Electron Devices, vol. ED-27, No. 6, June 1980.
In addition, a report published by R. Zuleeg titled “Complementary GaAs Logic” dated 4 August, 1985 is cited as prior art. The authors have also published the material in Electron Device Letters in 1984 in a paper titled “Double Implanted GaAs Complementary JFET's”.
A representative structure of a conventional n-channel JFET is shown in . The JFET is formed in an n-type substrate . It is contained in a p-well region marked . The body of the JFET is shown as , which is an n-type diffused region containing source (), channel (), and drain () regions. The gate region () is p-type, formed by diffusion into the substrate. Contacts to the source, drain, and gate regions are marked as , , and , respectively. The critical dimension of the JFET is the gate length, marked as . It is determined by the minimum contact hole dimension , plus the necessary overlap required to ensure that the gate region encloses the gate contact. The gate length is significantly larger than . This feature of construction of the prior art JFET limits the performance of these devices, since channel length is substantially larger than the minimum feature size. In addition, the capacitances of the vertical sidewalls of the gate diffusion to drain and source regions and respectively are also quite large. The gate-drain sidewall capacitance forms the Miller capacitance, a term known to those skilled in the art, and significantly limits the performance of the device at high frequencies.
A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
A method of building complementary logic circuits is disclosed using Junction Field Effect Transistors (JFETs) in silicon. an exemplary method is suited for deep submicron dimensions, such as below 65 nm.
A system of semiconductor devices having, for example, minimum feature sizes of 65 nm and below, is also disclosed. Methods and structures disclosed herein can build semiconductor devices and circuits which are similar to those used for CMOS devices. As such, exemplary embodiments can be inserted in an existing VLSI design and fabrication flow without any significant change in the overall system for designing and fabricating VLSI circuits. Exemplary attributes are as follows;
A complementary Junction Field Effect Transistor (JFET) disclosed herein is operated in the enhancement mode. As is known to those skilled in the art, enhancement mode, implies that the transistor is in the “OFF” state when the potential between the gate and the source terminals is zero. In this state, there is little or no current flow between drain and source when a positive (negative) bias is applied at the drain terminal of the n-channel (p-channel) JFET. As the potential at the gate is increased (decreased), the n-channel (p-channel) JFET enters the high conduction regime. In this mode, a finite current flows between the drain and the source upon application of positive (negative) bias at the drain. A limitation of known enhancement mode JFET devices is that their current drive is limited by the maximum gate voltage, which is less than one diode drop. A gate voltage in excess of one diode drop (the built-in potential) turns on the gate-channel diode which is an undesirable mode of operation for the JFET. This limitation can be resolved by, for example, limiting the biasing voltage, VDD, to less than one diode drop. The problem of low current drive of the JFET is addressed by scaling the channel length of the JFET to sub-100 nanometer dimensions. When the JFET gate length is less than 70 nanometers and the power supply voltage is 0.5 V, the current output of the complementary JFET devices and the switching speed of the inverters made with the complementary JFET devices compare favorably with known CMOS devices.
It should be noted that although the speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions, the maximum power supply voltage for the JFETs can still be limited to below a diode drop. To satisfy certain applications which require an interface to an external circuit driven to higher voltage levels, structures and methods to build CMOS devices are also disclosed. The CMOS devices described herein differ from known CMOS along the following points;
An exemplary circuit diagram of an inverter is shown in . The operating terminal voltages of the two transistors under ON and OFF conditions are shown in Table 1:
The operation of the circuit shown in can be remarkably similar to the operation of the corresponding CMOS circuit. Exemplary embodiments of JFETs described herein can operate at voltage levels which are similar to the voltage levels of the known CMOS technology. The input voltage varies between 0 and Vdd. The output voltage varies between Vdd and 0 in an inverse relationship to the input voltage. Thus, for the two states of the inverter, when the applied voltage at the input terminal is 0 and Vdd, the output voltage is Vdd and zero respectively. This can be achieved by the two transistors FT and FT being switched ON and OFF, as stated in Table 1 above.
JFETs operate by applying a control signal at the gate, which controls the conduction characteristics of the channel between the source and the drain. The gate forms a p-n junction with the channel. The voltage at the gate with respect to the source controls the width of the depletion region of the gate-to-channel junction. The undepleted part of the channel is available for conduction. Thus, the channel is turned ON and OFF by applying appropriate voltages at the gate and source terminals of the JFET transistor. Current will flow between the source and the drain when the channel is turned ON and the appropriate voltage is applied to the drain.
The JFET transistors FT and FT in the JFET inverter can function in a manner very similar to the MOS transistors in a CMOS inverter. The operation of a CMOS inverter is well known to those skilled in the art. The p-channel JFET (FT) is connected to the power supply at its source terminal. The n-channel JFET (FT) is connected to the ground at its source terminal. The drain terminals of the two transistors are connected together and to the output terminal of the gate. The gate of the p-channel JFET FT and the gate of n-channel JFET FT are connected together and to the input terminal of the gate, as shown in . This circuit configuration is called a CFET inverter in the remainder of this document. In general, gates formed in a similar manner with p-channel and n-channel JFETs are called CFET gates.
The functioning of the inverter is explained in greater detail here in order to reveal an exemplary full implementation. This is accomplished by first explaining the voltages at the source and the drain terminals of the transistor, which are shown in Table 2. In an exemplary and non-limiting illustration, the power supply voltage is fixed at 0.5V.
The gate of the p-channel JFET is made of n-type silicon and the channel is doped p-type. The doping profile of the p-channel JFET is designed to turn off conduction through the channel when the voltage on the gate terminal is at zero volts relative to the source terminal. This device is an enhancement mode device. This attribute of the p-channel JFET is due to the built-in potential at the p-n junction between the gate (p-type) and the channel (n-type). Since the source of the FT is tied to VDD at 0.5V, the external bias between the n-type channel and p-type gate is 0.0V when the gate of the FT is also at 0.5 V. This represents the FT in the OFF condition. As the bias at the gate of the p-channel transistor is decreased to 0.0V, the negative voltage between the gate and the source terminals changes to −0.5V, which causes the depletion layer to collapse and allows the flow of current from source to drain. This represents the FT in the ON condition.
Exemplary embodiments can limit gate current when FT is in the ON condition. The channel-to-gate diode is forward biased at 0.5 V under this condition, so there is a finite leakage current which flows through the gate of the transistor. It is termed the gate leakage. The magnitude of the gate leakage is controlled by the built-in potential across the gate-channel junction. The built-in potential limits the gate leakage current to a very small amount when this CFET inverter is operated with supply voltages (V) at or below 0.5V for silicon-based circuits. Thus, the CFET inverter works in a manner similar to the CMOS inverter in both design and operating characteristics. The limit for supply voltages may be different for other materials because of differences in the built-in potential. Similarly, the bias voltages for the n-channel JFET are reversed; the transistor is turned “OFF” when the gate-source bias is reduced to zero and it is turned on when the gate-source bias is equal to the supply voltage VDD, which is limited to 0.5V in order to restrict the gate current. The gate current of a typical gate-channel junction is projected in the range of 1 uA/cmto 100 mA/cm. In contrast, for an MOS transistor made with 45 nanometer lithography and appropriately scaled gate dielectric thickness, the gate current is projected to be in excess of 1000 A/cm.
The input capacitance of the JFET transistor is the junction capacitance of the diode formed by the gate-channel terminals. The capacitance of this diode is in the range of 10F/cmto 10F/cm, determined by the thickness of the depletion layer width of the junction, which is in the range of 100 angstroms to 3000 angstroms. The input capacitance of an MOS transistor made with 45 nanometer design rules and 10 angstrom thick oxide is an order of magnitude higher than the corresponding input capacitance of the JFET. This feature makes the JFET extremely attractive from the perspective of low power operation.
The JFET transistors also have a fourth electrical terminal, namely the well. One embodiment of the invention is described here with the well connected to the source terminal for both the JFETs, as shown in
A doping profile of the transistor at varying depths from the silicon surface through the gate () and channel () is shown in . The curve is an exemplary doping profile of the gate region starting from the silicon surface. Curves , , and represent the doping profile of the channel, well, and the bulk regions. For the n-JFET, is the doping profile of the p-type gate region, is the profile of the n-type channel region, is the profile of the p-type well region, and is the profile of the surrounding n-type bulk region. The gate-channel junction is given by , the channel-well junction is given by , and the well-bulk region junction is given by . The depth of the junction between gate and channel from the surface of silicon () is less than the depth of the junction between the channel and the p-well ().
Other methods for forming the p-type gate junction, such as ion-implantation are encompassed herein. Other methods to dope the gate, such as plasma immersion implant, as is well known to those skilled in the art, are also encompassed.
In , the Region is a slab of polysilicon which is doped heavily p-type and acts as the source for doping of the gate . The p-type gate is used to control the conduction across the channel from source to drain. By this novel construction technique, the gate is diffused in the channel region from heavily doped polysilicon which also forms an ohmic contact with the gate. This allows the polysilicon to be used to connect the gate to the external circuit.
The ohmic contact to the well is made by the well tap marked as object . The contacts to the four terminals of the JFET, namely well, source, gate, and drain are shown in also, as objects , , , and , respectively. The region underneath the p-well tap is doped heavily with p-type impurities to make good ohmic contact. The p-well is formed in an n-well marked as for applications where the p-well of the JFET has to be isolated. For applications where the p-well is connected to the ground potential, the need for the n-well is obviated. Both of these cases are encompassed herein.
The doping types are reversed for the p-channel JFET in relation to those described in and , i.e. the p-type regions are replaced by n-type regions and vice versa. It should be pointed out that doping the gate of the JFET with polycrystalline silicon is maintained for the p-channel JFET also.
An alternate embodiment of the JFET is shown in . This Figure shows the cross section of an n-channel JFET, which is very similar to an MOS transistor. The structure of the n-channel JFET is described here. It is implied that this structure will also be replicated for the p-channel JFET with appropriate changes in doping, as described in the paragraph above. The JFET is shown as object . The p-well in which the JFET is formed is marked as object . The isolation for the JFET is provided by a region filled with an insulating material such as silicon dioxide or other suitable materials in object . This structure is similar to the corresponding structure shown in . The heavily doped n-type regions form the source and drain region and are marked and , respectively. The channel region between source and drain is lightly doped n-type and is marked . The gate region is doped p-type and is marked . This region is diffused from the polysilicon with heavy p-type doping marked as . An insulating region marked is inserted here, surrounding the gate, consisting of a combination of silicon dioxide and nitride layers. This object is called a “spacer” in this document. In an exemplary embodiment, top surfaces of the regions , , and are covered with a highly conducting layer of one of the metallic compounds called silicides, marked as . The silicide layer is self aligned to the well tap, source, drain, and gate regions, implying that the silicide is formed only in the regions where there is exposed silicon or polysilicon. An exemplary purpose served by the spacer is that it isolates the source and drain regions from the gate region when self aligned silicides are formed. It also allows efficient distribution of current from the contact inside the device. The contacts to the well tap, source, drain, and gate regions are done in a manner similar to that in , and are marked as , , , and , respectively.
In an alternate embodiment of the JFET, as shown in , contacts to all the terminals of the JFET, namely source, gate, drain, and well, are all made with polysilicon. This structure has the desirable attribute of having contacts to all terminals at the same level. The n-channel JFET is made in a p-well marked , which is isolated from all sides by an insulated region . This structure is similar to the corresponding structure shown in . The source of the JFET is formed by a combination of heavily n-doped regions and . The drain of the JFET is also formed by a combination of heavily doped n-type regions and . The channel is a shallow n-type doped region between drain and source. The p-type gate region diffused in silicon is marked as . Blocks and are heavily n-type polysilicon doped regions. The region is formed by diffusing n-type impurities from the polysilicon into the silicon. Similarly, region is formed by diffusion of n-type impurities from the polysilicon region into the silicon. The gate region is formed by diffusion of the p-type impurities from the p-type polysilicon into the silicon. The regions and connect the source and the drain regions and , respectively, to the channel . The polysilicon regions marked as , and are in ohmic contact with regions , , and respectively. The regions and are formed by external doping such as ion implantation, plasma immersion implantation, or other similar doping methods. The well tap is formed by ohmic contact between the heavily p-doped polysilicon and the p-type region . The contacts to the transistor are made at the top of the objects , and and . In order to reduce ohmic contact resistance of these regions, self aligned silicide is formed on top of the polysilicon layer, marked as . In an alternate embodiment, contacts to the terminals of the transistor are made directly to the polysilicon.
In an alternate embodiment, the top surface of the silicon substrate is formed by epitaxial deposition of silicon-germanium alloy, which is doped appropriately to form the channel and the gate, shown in . The structure is built-in a well with isolation regions . An exemplary feature of this embodiment is that the channel of the JFET is formed on an epitaxially deposited layer of silicon-germanium alloy marked as object . The mobility of the silicon-germanium alloy is much higher than silicon, which increases the performance of the JFET, especially at high frequencies. This epitaxial layer is deposited on the transistor after the formation of the isolation structure on the wafer. The epitaxial layer can be deposited selectively in this embodiment on the islands where the channel is to be formed. The epitaxial layer for the channel of the nJFET is deposited in one step, and the epitaxial layer for the channel of the pJFET is deposited in the next step. In another embodiment, the epitaxial layer is deposited on the wafer prior to the formation of the isolation structure. In yet another embodiment, the channel region is formed by a strained silicon-germanium alloy. Another embodiment teaches the use of silicon-germanium-carbon to build the channel region of the JFETs. The terms silicon-germanium alloy and strained alloys are well known to those skilled in the art. The silicon-germanium alloy is formed by deposition of a mixture of silicon and germanium atoms epitaxially on the silicon substrate. The remaining structure of the JFET is similar to the structure shown in . The doping of the epitaxially deposited channel is controlled by external doping, such as ion implantation. Alternately, the epitaxially deposited material is doped during deposition by methods such as atomic layer epitaxy and similar techniques. The epitaxial deposition steps are also applicable to the JFET structures shown in .
Another embodiment, shown in , involves the use of a high band gap material such as silicon carbide or silicon-germanium carbide to form the gate contact region . This feature is implemented in order to increase the barrier height at the p-n junction formed at the gate -channel junction. The high band gap material of the gate contact region in proximity to the gate region effectively increases the barrier height at the p-n junction formed at the gate -channel junction. The higher gate-channel junction built-in potential reduces the saturation current across the junction, and allows an increase in the maximum voltage which can be applied to the gate-channel diode to forward bias it without causing a significant amount of gate current to flow across the diode. Since the maximum voltage at the gate is equal to the power supply voltage of the inverter, a higher power supply voltage becomes possible, increasing the drive strength of the transistors and resulting in faster switching of the inverter. As shown in for this embodiment, the polycrystalline silicon carbide material is used in place of polysilicon to form the electrodes. The use of a high band gap material such as polycrystalline silicon carbide reduces the leakage current of the gate junction when the gate-channel diode is weakly forward biased during the ON state of the transistor. Various phases of silicon carbide can be used for this purpose, namely 3C, 4H, and 6H. Further, various other electrode materials can be used to form a rectifying junction with the silicon substrate, including ternary alloys of silicon-germanium-carbon and various other compound semiconductors such as gallium-aluminum-arsenide-phosphide. In an alternate embodiment, use of materials for the gate such as silicon carbide is made along with epitaxially deposited high mobility materials such as silicon-germanium at the same time. The composition of the gate material is varied during deposition. The electrode extensions for source, drain, gate, and well tap, marked as , , , and , are made of high band gap semiconductor material such as silicon carbide. A self aligned conducting layer is formed on the top of these electrodes and is marked as . The polycrystalline semiconducting materials are doped appropriately, as described in the previous paragraphs. The other components of the transistors remain similar to the nJFET structure described in .
An exemplary embodiment teaches the use of a silicon-carbide layer near the surface of the silicon to a depth ranging from 10 Å to 1000 Å, followed by deposition of polysilicon to a depth of 10 Å to 2500 Å. The composition of the polycrystalline layer is varied to facilitate accurate monitoring of the etching process, in which the polycrystalline material is etched fast until the composition marking the bottom of the layer is detected and then slowly with a selective etching process until all the polycrystalline material is etched. Detailed explanation of the fabrication process using polycrystalline silicon carbide is explained later in this document.
Next, an exemplary but non-limiting method of building the complementary JFET structure as shown in is illustrated as the flow chart in . Each step in the flow chart is further illustrated in . Step is illustrated in . Step is illustrated in . Step is illustrated in . Step and are illustrated in . Step is illustrated in . Step is illustrated in . Step is illustrated in . Step is illustrated in . Step is illustrated in . Step is illustrated in . Step is illustrated in .
Next, a layer of polysilicon is deposited over the whole wafer, as shown in . The thickness of polysilicon deposited on the wafer varies between 100 Å and 10,000 Å. The polysilicon is selectively doped to form regions which will eventually become the source, drain, gate, and well contacts of the JFETs using photoresist as masks. The details of the photolithographic process are omitted here for the sake of brevity. As shown in , the region marked as is doped with a heavy boron implant to a dose ranging between 1×10/cmand 1×10/cm. It is designed to act as the contact for the well region of the n-JFET. Region is designed to act as the gate contact for the n-JFET. It is doped heavily p-type with the parameters similar to those of region . Regions and are doped heavily with n-type dopants (phosphorous, arsenic, and antimony) to a dose ranging between 1×10/cmand 1×10/cm
The p-JFET is formed with regions and acting as the source and drain contacts (p type), respectively, region as the gate (n type), and region as the contact to the well tap (n type). Regions and are doped with a heavy concentration of boron atoms to a dose ranging between 1×10/cmand 1×10/cmand are designed to act as the source and drain contacts of the pJFET respectively. Similarly, regions and are doped heavily n-type and are designed to act as gate and well contacts of pJFET. In an alternate embodiment, a layer of oxide is deposited on top of the polysilicon layer before doing the ion implantation. The thickness of this layer varies between 20 Å and 500 Å. In another embodiment, layers of oxide and nitride are deposited on top of the polysilicon prior to ion implantation, with the thickness of the oxide and nitride films varying between 10 Å and 500 Å.
After diffusion of the various regions of the JFETs into the silicon, the gate patterning process takes place. Using an optical lithographic process, a layer of an anti-reflective coating, followed by a layer of photoresist are coated on the wafer. The thickness of these layers depends upon the selection of the photoresist, as is known to those skilled in the art. The photoresist layer is exposed and various terminals are delineated in the photoresist, marked as in . Alternate embodiment includes other methods of patterning the photoresist, including imprint lithography and e-beam lithography. With the photoresist layer as the mask, the protective layer above the polysilicon is etched first. Next, the polysilicon layer is etched, with the grooves such as reaching the bottom of the polysilicon layer. This step isolates the various terminals electrically, as shown in . For patterning the photoresist, various processes such as optical lithography, immersion lithography, imprint lithography, direct write e-beam lithography, x-ray lithography, or extreme ultraviolet lithography are used.
The next process step consists of depositing a dielectric (oxide) layer, etching contact holes in the oxide layer, and forming contact holes for the source, drain, gate and well tap terminals, and continuing with the conventional metal interconnect formation process as practiced in the formation of semiconductor chips. A cross section of the wafer after dielectric deposition and contact hole etch is shown in . The metal deposition and etch is shown in .
This process can be adapted for making MOS transistors along with JFETs. One application of this adaptation is to include CMOS-compatible I/Os on the chip. The process to make MOS transistors is described next. shows the cross section of a wafer after the formation of the n-wells and p-wells for JFETs and MOSFETs. The threshold (V) adjust implants for the MOSFETs are also completed. In addition, the formation of channel regions for the JFETs is also completed. A layer of gate dielectric (oxide or nitrogenated oxide) is grown on the wafer. This layer of oxide is etched away from the wafer except in the regions surrounding the gate of the MOSFETs. This oxide layer is shown as object . In an alternate embodiment of this invention, a thin layer of amorphous silicon is deposited on top of the gate dielectric immediately after the oxide is grown. The thickness of this amorphous layer is sufficient to prevent damage to the underlying gate dielectric during the next photomasking and etching step. The preferred thickness of this amorphous silicon layer is between 10 Å and 5000 Å. In an alternate embodiment of the invention, the oxide layer is formed first, and the channel for the JFETs is formed afterwards.
Next, a layer of polysilicon is deposited on the wafer as shown in . The polysilicon layer is covered by a protective layer of oxide marked as . With photolithography to define certain regions on the wafer, a layer of photoresist is selectively removed from the wafer and the exposed areas are implanted with n-type and p-type dopants. This Figure shows the polysilicon layer with selectively doped regions. Region is doped p-type, region is doped n-type, region is doped p-type, and region is doped n-type. The parameters for doping these regions are the same as the parameters described in .
The next step is the definition of the gate and the remaining electrodes on polysilicon, as shown in . It is accomplished by first defining the pattern in a photoresist layer . Next, using the photoresist layer as a mask, the polysilicon layer is etched to define the electrodes. Region forms the well tap of the NMOS, region forms the source of the NMOS, region forms the gate of the NMOS, region forms the drain of the NMOS, region forms the source of the PMOS, region forms the gate of the PMOS, region forms the drain region of the drain of the PMOS, and region forms the well tap for the PMOS. After etching the polysilicon layer, a short oxidation cycle is executed to form an oxide on the surface of silicon with a thickness between 20 Å and 500 Å. Additional heat cycles are executed to diffuse the dopants into the silicon from the polysilicon in the drain, source, and the well tap regions while controlling the diffusion of the dopants from the polysilicon into the gate dielectric and into the channel region.
The complete flow for forming JFETs and MOSFETs on the same wafer is shown in . The MOS transistors fabricated in this manner can have advantages over the known methods of building MOS transistors, as described here:
Known MOS transistors have a spacer which is used to separate the highly doped source/drain regions from the gate. The dimensions of the spacer are dependent upon the vertical polysilicon dimension and other processing parameters, and are not laterally scalable. The current embodiment of the MOS transistor uses lithography to separate the source/drain and the gate region, making this structure laterally scalable.
Known MOS transistors have a lightly doped source and drain region under the spacer, which limits the injection efficiency of the source, or the maximum current which can be controlled by the transistor. The current embodiment of the MOS transistor uses the link region as the source and drain junctions and it allows the doping of this region to be controlled independently.
Known MOS transistors have symmetrical source and drain regions. This embodiment allows asymmetrical source and drain junctions to be formed by spacing the source and drain polysilicon contacts from the gate asymmetrically.
Known MOS transistors have varying contact depths to the source/drain and the gate terminals; the contacts to the source/drain terminals are made directly to silicon while the contact to the gate terminal is made to polysilicon which is elevated from the source/drain junctions. This embodiment of MOS transistors etches all the contact holes to the polysilicon, keeping the depth of all the holes the same.
Known MOS transistors compromise the short channel performance due to limitations imposed by a shallow source/drain junction and the silicide formation on top of these junctions. This embodiment of the MOS transistors removes this limitation by placing the silicide on top of the polysilicon for all the junctions. Also, the shallow source/drain junction in the silicon is formed by diffusion of dopants from the polysilicon, which is a slower and more controllable process.
This method to build JFETs and MOSFETs allows a planar surface to exist prior to contact hole etch. It also insures that the amount of polysilicon removed is limited, which can be important in achieving a uniform plasma etch. It is well known that the variation in the density of the polysilicon pattern on the silicon wafer is responsible for variation in the etch rate of polysilicon. In this method, this problem can be overcome by the fact that the pattern density of polysilicon is much higher than in conventional process technology. Also, the contacts to the various junctions are separated by the polysilicon layer, which makes it extremely convenient to form shallow source and drain junctions.
Steps in are further illustrated in .
The gate electrodes of the JFET and the MOS transistors are implanted with appropriate dopants. The gate regions of the NMOS transistor and the pJFET are doped heavily n-type with arsenic, phosphorus, or antimony. The gate electrode regions of the PMOS and the nJFET are implanted with p-type dopants, namely boron. The gate electrode regions are implanted with a heavy dose of the dopants in the range of 1×10/cmto 1×10/cm. An alternate embodiment of the invention includes multiple implant steps for forming the gate electrode region of the MOS and JFET transistors. The wafer is heated to distribute the dopants throughout the polysilicon layer.
A photomask is put on the wafer and the layer of polysilicon is etched to define the gate electrodes for the transistors, as is shown in . Object forms the gate of the NMOS transistor while the object forms the gate electrode of the nJFET transistor. The gate of the NMOS transistor is formed with n-type polysilicon while the gate of the nJFET is formed with p-type polysilicon. After defining the gate, a short oxidation cycle is executed to remove the damage from the surface of polysilicon. Layers of oxide and nitride are deposited next and etched anisotropically to form spacers adjacent to the gate electrodes. At the end of the spacer formation, the cross section of the wafer shows a gate electrode surrounded by spacers on both sides. The objects marked are the spacers surrounding the gate. It should be noted here that the polysilicon on the nJFET islands (object ) does not have a layer of oxide underneath to stop the etch. So, the polysilicon etching process has to be conducted very carefully so as not to over-etch the polysilicon and etch into the silicon. Process steps to prevent over-etching the polysilicon have been described earlier in this application.
Exemplary embodiments provide numerous advantages described herein. For example, compatibility with MOS can be achieved in accordance with exemplary embodiments. An exemplary comparison of NFET and NMOS is shown below. This is based upon Tof 10 Å for MOS; and Tof 720 Å for JFET (with corresponding channel doping 1×10/cm). This result in significant in input capacitance and related performance specifications, as shown in Table 1.
The gate region can have an impurity concentration doped from the gate electrode region.
In comparison to fabricating a MOS structure, the JFET structure can be manufactured with fewer processing steps. In addition to the elimination of the gate dielectric, the gate in a JFET can be fabricated by diffusing the dopants from polysilicon. Using a single critical masking step and simplified contact hole etch process (i.e., drop down to the same level), process complexity can be reduced. Furthermore, electron mobility enhancing technology developed for CMOS (e.g., strained lattice) can be applicable to the JFET devices disclosed herein.
In exemplary embodiments, the thickness of the depletion layer can be between about 100 Å to about 3000 Å during the application of the second voltage. The gate region can have a line-width of about 45 nm.
In an exemplary embodiment, a first JFET can be configured adjacent to a second JFET, wherein the channel region of the first JFET is n-type and the channel region of the second JFET is p-type. is an exemplary complementary FET (CFET), fabricated from two adjacent JFET devices previously described and embodied in and . illustrates two adjacent device JFET devices, one with an n-type channel and the other with a p-type channel.
Various devices currently utilize CMOS technology, for example, static logic gates, dynamic logic gates, pass logic gates and memories. These devices can be fabricated by incorporating JFET technology as described herein. The JFET can be incorporated into any number of circuits and/or devices including, but not limited to a memory device such as an SRAM.
In general, JFET devices with lower junction capacitance can reduce the propagation delay, in comparison to their CMOS counterparts. Propagation delay, T, can be computed from the following expression:
By setting dTd/h=0 and dTd/dk=0, yields:
In other words, the RCvalue for CFET exhibits an approximately ten-fold decrease or about a three-fold decrease in propagation delay.
and by substituting the expression for k and h into the expression describing power yields:
Thus, at optimal values of k and h, power is a function of Conly. In other words, power is independent of C. The above expressions are also described, by H. B. Bakoglu, PhD. Dissertation, Stanford University 1986, pp. 43-46, incorporated by reference in its entirety.
The following Table illustrates exemplary parameters of a CFET device versus those of a CMOS device for use in the exemplary repeater:
In alternate embodiments, where a plurality of JFET devices are configured in a repeater chain, a propagation delay is inversely proportional to a number of devices in the requester chain. In one example, the propagation delay can be less than 20 nanoseconds. Such a feature is illustrated in the graph.
In alternate embodiments of a JFET device described herein, the channel region can include at least a layer of strained material. For example, the strained material can be a strained silicon.
The semiconductor substrate can be formed of at least one of Si, GaAs, InP or any III-V material.
An advantage of an NFET device as described herein is reduced leakage current, in comparison to its NMOS counterpart, as illustrated in . The total leakage current is a sum of the following components: the sub-threshold current (I), the gate current (I) and junction tunneling current (I).
Transistors as described herein can, for example, be suitable for next generation telephone/PDA handsets having exemplary specifications as follows:
Power=0.1 W (idle)/5 W (active)
Chip area=1 cm2
Gate count=100 M
10% of the gates active at any time
Power per gate=500 nW
50% of the power dissipated as active power
Active power=250 nW=½CV2
Fabrication of handsets with CMOS devices involve the following exemplary characteristics: V=1.0 V, C=0.5 fF/gate and C=1.5 fF/μm (state of the art). In contrast, exemplary fabrication of handsets with CFET, can be implemented with the following exemplary characteristics: V=0.5 V, C=2.0 fF/gate and C=0.06 fF/μm (state of the art).
The following illustrates exemplary parameters of a next generation handset:
Chip area=1 cm
Gate count=100 M
10% of the gates active at any time
As illustrated in , for CMOS devices, the primary focus is on the fabrication of devices with the emphasis on performance, while minimizing area, rather than power consumption. However, the primary focus of JFET devices includes low power consumption, while maintaining an emphasis on performance and the minimization of area.
It will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restricted. The scope of the invention is indicated by the appended claims rather than the foregoing description and all changes that come within the meaning and range and equivalence thereof are intended to be embraced therein.