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Method of producing and operating a low power junction field effect transistor


Title: Method of producing and operating a low power junction field effect transistor.
Abstract: A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter. ...

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USPTO Applicaton #: #20090184734 - Class: $ApplicationNatlClass (USPTO) -
Inventors: Ashok Kumar Kapoor



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The Patent Description & Claims data below is from USPTO Patent Application 20090184734, Method of producing and operating a low power junction field effect transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

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The present application is a continuation of U.S. patent application Ser. No. 11/635,004, filed Dec. 7, 2006, which claims priority under 35 U.S.C. §119 to U.S. Provisional Application No. 60/748,089, filed Dec. 7, 2005, the entire contents of which are hereby incorporated by reference in their entirety.

TECHNICAL

FIELD OF THE INVENTION

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Integrated circuits and devices, and methods of producing and/or using such, are disclosed, such as MOS transistors and Junction Field Effect Transistors (JFETs) and circuits.

BACKGROUND OF THE INVENTION

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Very Large Scale Integrated Circuits are being scaled to smaller dimensions to gain greater packing density and faster speed in a continuation of the trend of the past thirty years. Currently, CMOS technology is being manufactured with sub-100 nanometer (nm) minimum dimensions in 2005. Scaling CMOS with the minimum line width below 100 nm presents numerous problems to designers of integrated circuits. A few of the problems of the scaled CMOS transistors below 100 nm are highlighted below; 1. Power dissipation in CMOS is a big problem due to the high switching load caused by the increase in gate capacitance per unit area as the thickness of the gate dielectric is scaled. 2. The thickness of the gate dielectric used in the MOS transistor has been scaled down to less than 20 angstroms. Thinning of the gate dielectric has resulted in a significant amount of current through the gate dielectric as voltage is applied to the gate electrode. This current is termed the gate leakage. 3. The transistors conduct a finite current between the drain and source even when the gate voltage is reduced to zero. This current is termed the source drain leakage. 4. The result of the effects described above is CMOS circuits which conduct a significant amount of current even when there is no activity (static current); this undermines a key advantage of CMOS. Because of the static current, the static power, or the power dissipated by the CMOS chip when there is no activity, has become quite large, and at temperatures close to 100 degrees centigrade, the static power dissipation can become nearly equal to the dynamic power dissipation in CMOS circuits. As the CMOS technology is scaled to 65 nm, the problem of leakage is becoming more severe. This trend continues as the technology is scaled further to line widths of 45 nm and below. 5. The lateral scaling of CMOS design rules has not been accompanied by vertical scaling of feature sizes, resulting in three dimensional structures with extreme aspect ratios. For instance, the height of the polysilicon gate has decreased only 50% while the lateral dimension of the polysilicon gate has been reduced by over 90%. Dimensions of the “spacer” (a component of a CMOS transistor which separates the gate from the heavily doped source and drain regions) are dependent upon the height of the polysilicon, so it does not scale in proportion to the lateral dimensions. Process steps which are becoming difficult with scaling of vertical dimensions include formation of shallow source and drain regions, their silicidation without causing junction leakage, and etching and filling of contact holes to the source and drain regions 6. It is well known to those skilled in the art to measure power supply leakage current as an effective screen for detecting defects introduced in the fabrication of the device. This method is sometimes referred to as the Iddq test by those skilled in the art. This method is effective for CMOS with the minimum line width above 350 nm. Scaling CMOS with the minimum line width below 350 nm increases the inherent leakage current to levels comparable to defect induced leakage current, rendering the Iddq test ineffective. Biasing the well voltage of the MOS device to eliminate the inherent leakage current introduces new elements of leakage such as gate leakage, junction tunneling leakage, etc.

The prior art in junction field effect transistors dates back to the 1950s when they were first reported. Since then, they have been covered in numerous texts such as “Physics of Semiconductor Devices” by Simon Sze and “Physics and Technology of Semiconductor Devices” by Andy Grove. Junction field effect devices were reported in both elemental and compound semiconductors. Numerous circuits with junction field effect transistors have been reported, as follows; such as:

Nanver and Goudena, “Design considerations for Integrated High-Frequency p-Channel JFET's”, IEEE Transactions Electron Devices, vol. 35, No. 11, 1988, pp. 1924-1933.

O. Ozawa, “Electrical Properties of a Triode Like Silicon Vertical Channel JFET”, IEEE Transcations Electron Devices vol. ED-27, No. 11, 1980, pp. 2115-2123.

H. Takanagi and G. Kano, “Complementary JFET Negative-Resistance Devices”, IEEE Journal of Solid State Circuits, vol. SC-10, No. 6, December 1975, pp. 509-515.

A. Hamade and J. Albarran, “A JFET/Bipolar Eight-Channel Analog Multiplexer”. IEEE Journal of Solid State Circuits, vol. SC-16, No. 6, December 1978.

K. Lehovec and R. Zuleeg, “Analysis of GaAs FET's for Integrated Logic”, IEEE Transaction on Electron Devices, vol. ED-27, No. 6, June 1980.

In addition, a report published by R. Zuleeg titled “Complementary GaAs Logic” dated 4 August, 1985 is cited as prior art. The authors have also published the material in Electron Device Letters in 1984 in a paper titled “Double Implanted GaAs Complementary JFET's”.

A representative structure of a conventional n-channel JFET is shown in FIG. 8. The JFET is formed in an n-type substrate 810. It is contained in a p-well region marked 815. The body of the JFET is shown as 820, which is an n-type diffused region containing source (832), channel (838), and drain (834) regions. The gate region (836) is p-type, formed by diffusion into the substrate. Contacts to the source, drain, and gate regions are marked as 841, 842, and 840, respectively. The critical dimension of the JFET is the gate length, marked as 855. It is determined by the minimum contact hole dimension 850, plus the necessary overlap required to ensure that the gate region encloses the gate contact. The gate length 855 is significantly larger than 850. This feature of construction of the prior art JFET limits the performance of these devices, since channel length is substantially larger than the minimum feature size. In addition, the capacitances of the vertical sidewalls of the gate diffusion to drain and source regions 861 and 862 respectively are also quite large. The gate-drain sidewall capacitance forms the Miller capacitance, a term known to those skilled in the art, and significantly limits the performance of the device at high frequencies.

SUMMARY

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OF THE INVENTION

A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.

BRIEF DESCRIPTION OF DRAWINGS

So that the manner in which the above recited features, advantages and objects are attained and can be understood in detail, a more particular description, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.

It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting as other equally effective embodiments will be apparent to those skilled in the art.

FIG. 1 is a diagram illustrating a complementary JFET inverter.

FIG. 2a is a diagram of a complementary JFET inverter with the well tied to the source.

FIG. 2b is a diagram of a complementary JFET inverter with the well tied to the gate.

FIG. 2c is a diagram of a complementary JFET inverter with the well tied to an external pad.

FIG. 3a is a diagram of the layout of a JFET.

FIG. 3b is a diagram of the cross section of a poly gate JFET corresponding to FIG. 3a.

FIG. 3c is a graph showing the doping profile of a JFET through the gate and the channel.

FIG. 4 is a cross section of a poly gate JFET similar to a conventional MOSFET.

FIG. 5 is a cross section of a poly gate planar JFET with all the contacts made through polysilicon.

FIG. 6 is a cross section of a poly gate planar JFET with the channel region grown epitaxially.

FIG. 7 is a cross section of a poly gate planar JFET with the channel region grown epitaxially and the polycrystalline semiconductor alloy gate comprising carbon, silicon, and germanium.

FIG. 8 is a cross section of a conventional n-channel JFET.

FIG. 9 is a flow chart of building the complementary JFET structure as shown in FIG. 5. Each step of the flow chart is further illustrated in FIG. 10-20.

FIG. 10 is the cross section of the silicon wafer after the formation of the isolation region.

FIG. 11 is the cross section of the silicon wafer after the formation of the n-well and the p-well.

FIG. 12a is the cross section of the silicon wafer after the formation of the channel region of nJFET.

FIG. 12b is the cross section of the silicon wafer after the formation of the channel region of the pJFET.

FIG. 13 is the cross section of the silicon wafer after polysilicon deposition and selective doping of polysilicon.

FIG. 14 is the cross section of the silicon wafer after deposition of a protective coating on the polysilicon layer.

FIG. 15 is the cross section of the silicon wafer after polysilicon definition by photolithography and etching.

FIG. 16a is the cross section of the silicon wafer after doping the link region between the gate and the drain/source of the p-channel JFET.

FIG. 16b is the cross section of the silicon wafer after doping the link region between the gate and the drain/source of the n-channel JFET.

FIG. 17 is the cross section of the silicon wafer after filling the empty space between the polysilicon structures and then performing planarization.

FIG. 18 is the cross section of the silicon wafer after formation of self aligned silicide on the exposed polysilicon surfaces.

FIG. 19 is the cross section of the silicon wafer after deposition of the dielectric layer on polysilicon and the subsequent etching of contact holes.

FIG. 20 is the cross section of the silicon wafer after metal deposition and definition.

FIG. 21-24 describe the formation of a MOS transistor using the process adapted from FIG. 9.

FIG. 21 shows the cross section of the silicon wafer after formation of isolation regions, well structures, threshold implants and gate dielectric. The gate dielectric is grown and etched from the wafer except for regions surrounding the MOS gate region.

FIG. 22 shows the cross section of the silicon wafer after polysilicon deposition, polysilicon doping and formation of a protective layer on top of the polysilicon.

FIG. 23 shows the cross section of the silicon wafer after polysilicon definition.

FIG. 24 shows the cross section of the silicon wafer after the link region is formed between the gate and the source/drain by ion implantation.

FIG. 25 shows the complete flow for forming JFETs and MOSFETs on the same wafer. Each step is further illustrated in FIG. 26-30.

FIG. 26 shows the cross section of the silicon wafer after the n-well and the p-well have been formed.

FIG. 27 shows the cross section of the silicon wafer after the channel for the JFET is formed.

FIG. 28 shows the cross section of the silicon wafer after the channel for MOS is formed.

FIG. 29 shows the cross section of the silicon wafer after source and drain regions for MOS and JFET are formed.

FIG. 30a shows the cross section of the silicon wafer after the contact holes and metal connections are formed.

FIG. 30b shows the layout of the NMOS and nJFET after the contact holes and metal connections are formed.

FIG. 31 shows an exemplary complementary poly FET or CFET.

FIG. 32 shows an exemplary propagation delay associated with an exemplary repeater insertion configured using a transistor according to an exemplary embodiment described herein.

FIG. 33 shows an exemplary delay and power comparison associated with an exemplary CFET configured in accordance with an exemplary embodiment versus CMOS.

FIG. 34 shows an exemplary propagation delay for CFET versus CMOS versus buffer segments (width).

FIG. 35 shows an exemplary comparison sub-threshold conduction of JFET versus MOS.

FIGS. 36a and 36b show a comparison of gate current in an NFET (FIG. 36a) versus NMOS (FIG. 36b).

FIG. 37 shows an exemplary Figure of merit associated with CMOS, while

FIG. 38 shows an exemplary Figure of merit associated with a transistor configured in accordance with exemplary embodiments described herein.

DETAILED DESCRIPTION

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OF THE INVENTION

A method of building complementary logic circuits is disclosed using Junction Field Effect Transistors (JFETs) in silicon. an exemplary method is suited for deep submicron dimensions, such as below 65 nm.

A system of semiconductor devices having, for example, minimum feature sizes of 65 nm and below, is also disclosed. Methods and structures disclosed herein can build semiconductor devices and circuits which are similar to those used for CMOS devices. As such, exemplary embodiments can be inserted in an existing VLSI design and fabrication flow without any significant change in the overall system for designing and fabricating VLSI circuits. Exemplary attributes are as follows; 1. It allows significant reduction in the power dissipation of the circuit. 2. It allows significant reduction in the gate capacitance. 3. It allows significant reduction in the leakage current at the gate. 4. It allows significant reduction in the leakage current between source and drain. 5. It allows significant simplification of the VLSI manufacturing process. 6. It leverages the design infrastructure developed for CMOS technology. It is contemplated that all complex logic functions available in prior art CMOS cell library can be implemented with the devices disclosed herein. These complex logic functions include but not limited to inverter, nand, nor, latch, flip-flop, counter, multiplexer, encoder, decoder, multiplier, arithmetic logic unit, programmable cell, memory cell, micro-controller, JPEG decoder, and MPEG decoder.


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stats Patent Info
Application #
US 20090184734 A1
Publish Date
07/23/2009
Document #
12349350
File Date
01/06/2009
USPTO Class
326122
Other USPTO Classes
326112
International Class
/
Drawings
39


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