Packet switch

The present application is a continuation application of U.S. patent application Ser. No. 10/074,015, filed on Feb. 14, 2002.

The present invention relates to an input buffering switch for use in a packet switching system, more particularly to a virtual output queuing (VOQ) in the input buffering switch.

In a recent packet switching system, so as to realize a high-speed and high-capacity switch, sometimes is employed an input buffering switch having N kinds of input and N kinds of output (N is a natural number, hereinafter, likewise), and yet having N virtual output queuing (VOQ).

FIG. 9 is a block diagram illustrating a configuration of a conventional input buffering type packet switch using the virtual output queuing (VOQ).

As shown in the same drawing, a packet switch 100 comprises first to N-th input interface sections 101-1 to 101-N that input data, first to N-th output interface sections 102-1 to 102-N that output data, a data switching element 103 that makes switching for data input from the input interface sections 101-1 to 101-N to transfer it to the output interface sections 102-1 to 102-N, and a switch scheduler 104 that controls the data switching element 103.

Each of the first to the N-th input interface sections 101-1 to 101-N comprises a destination address resolution and forwarding engine section (FE) 105, a packet assembly and disassembly section (PAD) 106, and a virtual output queuing (VOQ) 107.

The destination address resolution and forwarding engine section 105 makes solution for a destination of a packet sent from a transmission line and a class to which it belongs. The packet assembly and disassembly section (PAD) 106 splits the packet into cells with a fixed size. In this packet switch 100, a bandwidth of the transmission line and the switch within a device is managed by cell unit.

Assume that the class number, which is handled in the packet switching system, is K, the virtual output queuing (VOQ) 107 has K×N kinds of output, and logical queues that corresponded to each class. Each cell disassembled in the packet assembly and disassembly section (PAD) 106 is stored in a buffer within the virtual output queuing (VOQ) 107 responding to the destination or the class.

The data switching element 103 is configured of N×N cross point switches.

Based on information obtained from the first to N-th input interface sections 101-1 to 101-N, the switch scheduler 104 meditates cell transfer request of these first to N-th input interface sections 101-1 to 101-N, and gives cell transfer permission to respective virtual output queuings (VOQs) 107.

Also, the switch scheduler 104 was adapted so that, by controlling the data switching element 103, the cells output from the virtual output queuing (VOQ) 107 are switched over to the corresponding destination out of the output interface sections 102-1 to 102-N

At this moment, C cells (C is a natural number) are transferred within the switch as one unit. C is a fixed value that is decided responding to a system. In this specification, this one unit\'s cell is referred to as a super cell.

Each of the first to N-th output interface sections 102-1 to 102-N was configured of a virtual input queue (VIQ) 108 and a packet assembly section (PAD) 109.

The virtual input queue (VIQ) 108 also includes KN kinds of output, and logical queues that corresponded to each class.

The super cells sent from the data switching element 103 are stored in the virtual input queue (VIQ) 108, which corresponds to a input interface number and a class number of a sending end, out of the virtual input queues (VIQs) 108 within the first to N-th output interface sections 102-1 to 102-N, and are returned to an original packet by the packet assembly section (PAD) 109.

Hereinafter, the packets are output to the transmission line.

FIG. 10 is a block diagram illustrating a configuration of the virtual output queuing (VOQ) 107.

The virtual output queuing (VOQ) 107 comprises a VOQ buffer 120 and a VOQ controlling section 130.

The VOQ buffer 120 comprises first to N-th buffers by output ports 121-1 to 121-N. Assume that the class number, which is handled in the packet switching system, is K, the first to N-th buffers by output ports 121-1 to 121-N have logical queues that corresponded to the K classes.

The VOQ controlling section 130 was configured of a destination information allocation section 131 and first to N-th VOQ controlling sections by output ports 132-1 to 132-N.