Multi-port semiconductor memory device having variable access paths and method therefor

The above-referenced application is a Continuation of U.S. Ser. No. 11/466,389, filed on Aug. 22, 2006, now pending, which claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 2005-127534, filed Dec. 22, 2005, the disclosure of which is hereby incorporated herein by reference in its entirety.

1. Technical Field

The invention relates to multi-port semiconductor memory devices having variable access paths and, more particularly, to a semiconductor memory device and a method for performing a normal operation or a test operation by variably controlling access paths between a plurality of input/output ports and a plurality of memory areas.

2. Discussion of Related Art

In general, semiconductor memory devices such as random access memories (RAMs) include one port having a number of input/output pin sets in order to communicate with an external processor.

FIG. 1 illustrates a conventional semiconductor memory device having four memory banks and a single input/output port. The conventional semiconductor memory device includes a memory array 10 having four memory banks 10a, 10b, 10c and 10d, and a port control unit 20 for controlling a single input/output port. The port control unit 20 includes control circuits for controlling a command signal, an address signal, a data signal, and other signals input or output through the input/output port. All of the memory banks 10a, 10b, 10c and 10d are accessed through the port control unit 20. The arrows indicate the access paths.

The conventional semiconductor memory device having a single input/output port has problems with access speed and access efficiency. For example, to perform a first operation of storing first data in the A bank 10a and a second operation of reading second data from the B bank, which is distinct from the first operation, the semiconductor memory device must perform the operations sequentially, the first operation and then the second operation or vice versa. This is not suitable for high speed and high efficiency.

For higher speed and greater efficiency, a multi-port semiconductor memory device that performs communication through a plurality of processors and has memory cells that can be accessed through a plurality of input/output ports has been developed. An example of such a conventional multi-port semiconductor memory device is disclosed in U.S. Pat. No. 5,815,456, Sep. 29, 1998.

Generally, the conventional multi-port semiconductor memory device may have several structures to enable accessing of memory cells. Three representative structures include: (1) a structure allowing all memory cells to be accessed through any of a plurality of input/output ports; (2) a structure allowing each memory cell to be accessed only through fixed input/output ports; and (3) a structure allowing specific memory cells to be accessed only through fixed input/output ports and any remaining memory cells to be accessed through any ports.