Plated pillar package formation

This application is a Divisional of U.S. patent application Ser. No. 11/675,731, filed Feb. 16, 2007, the entire disclosure of which is incorporated herein by reference.

The present invention relates to electrical connections and, more particularly, to a process of forming a package for such electrical connections.

U.S. patent application Ser. Nos. 11/329,481, 11/329,506, 11/329,539, 11/329,540, 11/329,556, 11/329,557, 11/329,558, 11/329,574, 11/329,575, 11/329,576, 11/329,873, 11/329,874, 11/329,875, 11/329,883, 11/329,885, 11/329,886, 11/329,887, 11/329,952, 11/329,953, 11/329,955, 11/330,011 and 11/422,551, incorporated herein by reference, describe various techniques for forming small, deep vias in, and electrical contacts for, semiconductor wafers. Our techniques allow for via densities and placement that was previously unachievable and can be performed on a chip, die or wafer scale. However, if these techniques are used to form high density interconnects, there is presently no “off the shelf” or low cost commercially available packaging that can be used with them.

There is therefore a present need for low cost packaging that can be used with such high density interconnects.

According to an exemplary embodiment, a device includes a first plurality of interconnects, a first fill material surrounding the first plurality of interconnects, a first plurality of traces, and a first chip. The first plurality of interconnects extend from a first side of the fill material to an opposite side of the fill material. Each of the traces is connected to at least two of the first plurality of interconnects. The first chip is coupled to at least one of the first plurality of traces.

According to another exemplary embodiment, a device includes a first plurality of interconnect pillars, a first fill material surrounding the first plurality of interconnect pillars, a second plurality of interconnect pillars, and a second fill material surrounding the second plurality of interconnect pillars. The first plurality of interconnect pillars extend from a first side of the first fill material to an opposite side of the first fill material. The second plurality of interconnect pillars extend from a first side of the second fill material to an opposite side of the second fill material. At least one of the first plurality of interconnect pillars is coupled to at least one of the second plurality of interconnect pillars.

According to another exemplary embodiment, a device includes a first plurality of interconnect pillars, a first fill material surrounding the first plurality of interconnect pillars, a first chip, a second plurality of interconnect pillars, and a second fill material surrounding the second plurality of interconnect pillars. The first plurality of interconnect pillars extend from a first side of the first fill material to an opposite side of the first fill material. The second plurality of interconnect pillars extend from a first side of the second fill material to an opposite side of the second fill material. The first chip is coupled to at least one of the first plurality of electrically conductive pillars and to at least one of the second plurality of electrically conductive pillars.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates, in simplified form, a portion of a substrate 100 that will serve as the base for the process described herein;

FIG. 2 illustrates, in simplified form, the portion of the substrate 100 after a seed layer has been deposited by metalizing;

FIG. 3 illustrates, in simplified form, the portion of the substrate of FIG. 2 in which a photoresist has been applied and patterned to create openings down to the seed layer;

FIG. 4 illustrates, in simplified form, the portion of the substrate after plating is complete;

FIG. 5 illustrates, in simplified form, the portion of the substrate after removal of the photoresist;

FIG. 6 illustrates, in simplified form, the portion of the substrate after the package material is fully hardened;

FIG. 7 illustrates, in simplified form, the package after removal of the substrate and seed layer;

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