Semiconductor device and method for manufacturing a semiconductor device

This invention refers to embodiments of semiconductor devices and methods for their production, particularly the electrical connection between a semiconductor chip and its supporting structure.

In the production of semiconductor devices, small contact elements on the semiconductor chip have to be connected to electrical terminals which provide a contact to the outside world. These connections are generally realized as part of the package or encapsulation of the semiconductor chip, e.g. by providing a metallization layer on a face of the chip which provides conducting elements or lines connecting the contact elements of the chip to contact elements on an outer face of the package, e.g. solder balls. Especially with high pin counts, the problem frequently occurs that the high number of conducting lines in the layer cannot be arranged without crossings between at least some of the lines. In a single metallization layer, a crossing of two lines can not be realized because this would cause an electrical shortcut between the lines. Hence, in this case a second metallization layer has to be provided in order to arrange the connections between the chip and the contact elements to the outside.

According to an embodiment, a semiconductor device is provided. It includes a semiconductor chip which includes a first conducting element. A second conducting element outside the semiconductor chip is electrically connected to the first conducting element arranged at a first location. A third conducting element outside the semiconductor chip is electrically connected to the first conducting element at a second location. A fourth conducting element is also provided arranged outside the semiconductor chip. In a vertical projection of the fourth conducting element on the chip, the projection crosses the first conducting element between the first location and the second location.

According to a further embodiment, a semiconductor device is provided. It includes a semiconductor chip including at least two contact elements and a first conducting element located in the chip, and a layer of conducting elements arranged adjacent the chip, which include a contact region providing an interface to the outside of the semiconductor device. It further includes second and third conducting elements connected to the first conducting element located in the chip via contact elements, so that the second and third conducting elements are electrically connected via the first conducting element, and wherein the second conducting element is connected to the contact region. According to a further embodiment, there is provided a method of manufacturing semiconductor devices, which includes providing at least two semiconductor chips that each comprise a first conduction line, covering the at least two semiconductor chips with mold material, applying a metallization layer over the at least two semiconductor chips and the mold material such that the metallization layer contacts each of the first conduction lines at at least two separated locations, and separating the at least two semiconductor chips from each other after the application of the metallization layer.

According to a further embodiment, there is provided a method of manufacturing semiconductor devices, which includes providing a semiconductor chip having a first conducting element, which is connected to two contact elements on a face of the chip, and providing a layer of conducting elements on a face of the chip, wherein a second conducting element and a third conducting element of the layer of conducting elements are connected to the first conducting element located in the chip via contact elements, so that the second and third conducting elements are electrically connected via the first conducting element, and a vertical projection of a fourth conducting element of the layer of conducting elements crosses the first conducting element.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

A full and enabling disclosure of the present invention, including the best mode thereof, to one of ordinary skill in the art, is set forth more particularly in the remainder of the specification, including reference to the accompanying figures. Therein:

FIGS. 1a-1b shows a semiconductor device.

FIG. 2a shows a schematic cross-sectional view of the semiconductor device.

FIG. 2b shows a schematic perspective view of the semiconductor device.

FIG. 3a shows a cross-sectional view of a semiconductor device according to an embodiment of the invention.

FIG. 3b shows a schematic view of a semiconductor device according to an embodiment of the invention.

FIG. 4a-4b show a further semiconductor device.

FIG. 5a-5b show a detailed view of a semiconductor device according to an embodiment of the invention.

FIG. 6a-6b show a semiconductor wafer and a reconstituted wafer according to an embodiment of the invention.

FIG. 7a-7i show process steps according to an embodiment of the invention.

FIG. 8 shows an embodiment of a semiconductor device according to an embodiment of the invention.

FIG. 9 shows a further embodiment of a semiconductor device according to an embodiment of the invention.

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