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06/25/09 - USPTO Class 716 | 1 views | #20090164966 | Prev - Next | About this Page

Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit

Title: Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20090164966, Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit.

What is claimed is:

1. A computer program product in a computer-readable medium for efficiently producing a description of a logic function in m-ary decision representations, said computer program product comprising: a tangible computer-readable storage medium; instructions on the tangible computer-readable storage medium, when executed by a computer, for setting a first size limit for a first set of one or more m-ary decision representations describing a logic function; instructions on the tangible computer-readable storage medium, when executed by a computer, for setting a second size limit for a second set of one or more m-ary decision representations describing a logic function; instructions on the tangible computer-readable storage medium, when executed by a computer, for building said first set of m-ary decision representations of said logic function with one of the set of a depth-first technique or a breadth-first technique until said first size limit is reached; instructions on the tangible computer-readable storage medium, when executed by a computer, for building a second set of m-ary decision representations of said logic function with the other of the set of a depth-first technique or a breadth-first technique until said second size limit is reached; instructions on the tangible computer-readable storage medium, when executed by a computer, for, in response to determining that a union of first set and said second set of m-ary decision representations do not describe said logic function, for increasing said first size limit, for increasing said second size limit, and for repeating said instructions for building said first set and said instructions for building said second set; and instructions on the tangible computer-readable storage medium, when executed by a computer, for, in response to determining that said union of said first set of m-ary decision representations and said second set of m-ary decision representations describes said logic function, reporting the union of said first set of m-ary decision representations and said second set of m-ary decision representations to an output file.

2. The computer program product of claim 1, further comprising: instructions on the tangible computer-readable storage medium, when executed by a computer, for, in response to determining, during execution of one of the set of said instructions for building said first set of m-ary decision representations or said instructions for building said second set m-ary decision representations, that the union of said first set of m-ary decision representations and said second set of m-ary decision representations describes said logic function, suspending execution of said one of the set of said instructions for building said first set of m-ary decision representations or said instructions for building said second set m-ary decision representations and reporting the union of said first set of said first set of m-ary decision representations and said second set of m-ary decision representations.

3. The computer program product of claim 1, wherein: said instructions for increasing said first size limit further instructions on the tangible computer-readable storage medium, when executed by a computer, for doubling said first size limit; and said instructions for increasing said second size limit further comprise instructions on the tangible computer-readable storage medium, when executed by a computer, for doubling said second size limit.

4. The computer program product of claim 1, wherein: said instructions for building said first set of m-ary decision representations of said logic function further comprise instructions on the tangible computer-readable storage medium, when executed by a computer, for building a first set of binary decision representations of said logic function; and said instructions for building said second set of m-ary decision representations of said logic function further comprise instructions on the tangible computer-readable storage mediums when executed by a computer, for building a second set of binary decision representations of said logic function.

5. The computer program product of claim 1, wherein: said instructions for building said first set of m-ary decision representations of said logic function further comprise instructions on the tangible computer-readable storage medium, when executed by a computer, for building a first set of m-ary decision diagrams of said logic function; and said instructions for building said second set of m-ary decision representations of said logic function further comprise instructions on the tangible computer-readable storage medium when executed by a computer, for building a second set of m-ary decision diagrams of said logic function.

6. The computer program product of claim 1, wherein: said instructions for determining that said union of said first set of m-ary decision representations and said second set of m-ary decision representations describes said logic function further comprise instructions on the tangible computer-readable storage medium, when executed by a computer, for determining that said union of said first set of m-ary decision representations and said second set of m-ary decision representations contains binary decision diagrams for all sinks in said logic function.

7. The computer program product of claim 1, wherein: said instructions for building a second set of m-ary decision representations of said logic function with the other of the set of a depth-first technique or a breadth-first technique until said second size limit is reached further comprise instructions on the tangible computer-readable storage medium, when executed by a computer, for, in response to determining that said first set does not describe said logic function, building a second set of m-ary decision representations of said logic function with the other of the set of a depth-first technique or a breadth-first technique until said second size limit is reached.

8. The computer program product of claim 1, wherein: said instructions for determining that said first set do not describe said logic function further comprise instructions on the tangible computer-readable storage medium, when executed by a computer, for determining that said first set of m-ary decision representations does not contain binary decision diagrams for all sinks in said logic function; and said instructions for determining that a union of first set and said second set of m-ary decision representations do not describe said logic function further comprise instructions on the tangible computer-readable storage medium, when executed by a computer, for determining that said union of said first set of m-ary decision representations and said second set of m-ary decision representations does not contain binary decision diagrams for all sinks in said logic function.

Brief Patent Description - Full Patent Description - Patent Claims

Click on the above for other options relating to this Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit patent application.

Patent Applications in related categories:

20090288059 - Clustering and fanout optimizations of asynchronous circuits - Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is ...

20090288058 - Power aware asynchronous circuits - Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token ...

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Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit
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Method and system for implementing top down design and verification of an electronic design
Industry Class:
Data processing: design and analysis of circuit or semiconductor mask

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