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06/25/09 - USPTO Class 716 | 1 views | #20090164965 | Prev - Next | About this Page

Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit

Title: Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20090164965, Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit.

What is claimed is:

1. A system for efficiently producing a description of a logic function in m-ary decision representations, said system comprising: means for setting a first size limit for a first set of one or more m-ary decision representations describing a logic function; means for setting a second size limit for a second set of one or more m-ary decision representations describing a logic function; means for building said first set of m-ary decision representations of said logic function with one of the set of a depth-first technique or a breadth-first technique until said first size limit is reached; means for building a second set of m-ary decision representations of said logic function with the other of the set of a depth-first technique or a breadth-first technique until said second size limit is reached; means, in response to determining that a union of first set and said second set of m-ary decision representations do not describe said logic function, for increasing said first size limit, for increasing said second size limit, and for repeating said step of building said first set and said step of building said second set; and means, in response to determining that said union of said first set of m-ary decision representations and said second set of m-ary decision representations describes said logic function, for reporting the union of said first set of m-ary decision representations and said second set of m-ary decision representations to an output file.

2. The system of claim 1, further comprising: means, in response to determining, during one of the set of said step of building said first set of m-ary decision representations or said step of building said second set m-ary decision representations, that the union of said first set of m-ary decision representations and said second set of m-ary decision representations describes said logic function, suspending said one of the set of said step of building said first set of m-ary decision representations or said step of building said second set m-ary decision representations and reporting the union of said first set of said first set of m-ary decision representations and said second set of m-ary decision representations.

3. The system of claim 1, wherein: said means for increasing said first size limit further comprises means for doubling said first size limit; and said means for increasing said second size limit further comprises means for doubling said second size limit.

4. The system of claim 1, wherein: said means for building said first set of m-ary decision representations of said logic function further comprises means for building a first set of binary decision representations of said logic function; and said means for building said second set of m-ary decision representations of said logic function further comprises means for building a second set of binary decision representations of said logic function.

5. The system of claim 1, wherein: said means for building said first set of m-ary decision representations of said logic function further comprises means for building a first set of m-ary decision diagrams of said logic function; and said means for building said second set of m-ary decision representations of said logic function further comprises means for building a second set of m-ary decision diagrams of said logic function.

6. The system of claim 1, wherein: said means for determining that said union of said first set of m-ary decision representations and said second set of m-ary decision representations describes said logic function further comprises means for determining that said union of said first set of m-ary decision representations and said second set of m-ary decision representations contains binary decision diagrams for all sinks in said logic function.

7. The system of claim 1, wherein: said means for building a second set of m-ary decision representations of said logic function with the other of the set of a depth-first technique or a breadth-first technique until said second size limit is reached further comprises means, in response to determining that said first set does not describe said logic function, building a second set of m-ary decision representations of said logic function with the other of the set of a depth-first technique or a breadth-first technique until said second size limit is reached.

8. The system of claim 1, wherein: said means for determining that said first set do not describe said logic function further comprises means for determining that said first set of m-ary decision representations does not contain binary decision diagrams for all sinks in said logic function; and said means for determining that a union of first set and said second set of m-ary decision representations does not describe said logic function further comprises means for determining that said union of said first set of m-ary decision representations and said second set of m-ary decision representations does not contain binary decision diagrams for all sinks in said logic function.

Brief Patent Description - Full Patent Description - Patent Claims

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Patent Applications in related categories:

20090293036 - Hardware description language and a system and methods for electronic design - A Hardware Description Language (HDL) comprising of a plurality of object commands, a plurality of compile commands and a plurality of comment styles is used in methods of electronic circuit design. An object command in the HDL defines a logic object, which can be as simple as a piece of ...

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Previous Patent Application:
High-level synthesis apparatus, high-level synthesis system and high-level synthesis method
Next Patent Application:
Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit
Industry Class:
Data processing: design and analysis of circuit or semiconductor mask

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