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06/25/09 - USPTO Class 716 | 1 views | #20090164955 | Prev - Next | About this Page

Method for verifying safety apparatus and safety apparatus verified by the same

Title: Method for verifying safety apparatus and safety apparatus verified by the same

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20090164955, Method for verifying safety apparatus and safety apparatus verified by the same.

What is claimed is:

1. A verification method for verifying a safety apparatus including a programmable logic device, the programmable logic device including a plurality of functional elements, the method comprising the steps of: verifying on actual hardware that all outputs of a logic pattern are produced normally in response to all inputs of the logic pattern of each of the plurality of functional elements in advance; generating a plurality of functional elements, each the same as a different one of the plurality of functional elements verified on the actual hardware, using a predetermined hardware description language; independently logic-synthesizing each of the generated functional elements into a plurality of first net lists; generating a connection function among the generated functional elements using the predetermined hardware description language; logic-synthesizing the generated connection function into a second net list corresponding to the connection function; synthesizing the plurality of first net lists with the second net list to generate a third net list; writing a logic circuit into the programmable logic device on the basis of the third net list; and verifying on the programmable logic device including the written logic circuit that the operation of the programmable logic device is normal.

2. The verification method according to claim 1, further comprising the step of: verifying connections among the functional elements on the basis of the generated third net list.

3. The verification method according to claim 2, wherein the step of verifying connections among the functional elements includes the sub-step of: visualizing and displaying a logic circuit realizing the functional elements and the connection function on the basis of data of the generated third net list so as to verify that connections among the functional elements are correct on the basis of the displayed logic circuit and a specification defining the connection function.

4. The verification method according to claim 2, wherein the step of verifying connections among the functional elements includes the sub-step of: visualizing and displaying a connection circuit realizing the connection function so as to verify that connections among the functional elements are correct on the basis of the displayed connection circuit and a connection function represented by the predetermined hardware description language.

5. The verification method according to claim 1, further comprising the step of: simulating the operation of the programmable logic device on the basis of data of the generated third net list so as to verify that the operation of the programmable logic device is normal; wherein the step of simulating the operation of the programmable logic device includes a sub-step of evaluating a delay time of a logic circuit disposed between flip-flop devices operating in synchronization with the same clock by simulation so as to verify that the evaluated delay time is less than or equal to 50% of the period of the clock in a standard use environment.

6. The verification method according to claim 5, wherein the simulation of the delay time in the step of simulating the operation of the programmable logic device includes a simulation whose effectiveness is verified in advance using an appropriate net list for evaluation and a programmable logic device written on the basis of the net list for evaluation.

7. The verification method according to claim 1, wherein the step of verifying on actual hardware includes the sub-steps of: evaluating a delay time of a logic circuit disposed between flip-flop devices operating in synchronization with the same clock by simulation; and if the evaluated delay time is greater than 50% of the period of the clock in a standard use environment, verifying the programmable logic device on actual hardware while applying a use environment causing the delay time to be maximum to the programmable logic device so as to verify that the operation of the programmable logic device is normal.

8. The verification method according to claim 1, wherein the step of verifying on actual hardware includes toggle coverage testing, the toggle coverage testing including the sub-steps of: computing the total number of connection lines among the functional elements in advance; inputting a predetermined logic pattern into the programmable logic device while sequentially changing the logic pattern; computing the number of connection lines whose logical value is changed in accordance with the change in the input logic pattern; computing toggle coverage that is a ratio of the number of connection lines whose logical value is changed to the total number of connection lines; and verifying that the toggle coverage is greater than or equal to a predetermined value.

9. The verification method according to claim 8, wherein the toggle coverage testing includes testing for computing the total number of connection lines while removing a connection line connected to ground and a connection line connected to a power supply from the total number of connection lines.

10. The verification method according to claim 8, wherein the toggle coverage testing includes testing for computing the total number of connection lines while removing a connection line whose output logical value is apparently a fixed value regardless of an input logical value from the viewpoint of design.

11. The verification method according to claim 8, wherein the toggle coverage testing includes the sub-steps of: sequentially inputting the logic pattern into the actual programmable logic device and a simulated programmable logic device that simulates the actual programmable logic device in parallel so as to monitor that the output of the actual programmable logic device is normal; monitoring the change in a logical value of a connection line inside the simulated programmable logic device so as to compute the number of connection lines whose logical value is changed; sequentially computing the toggle coverage in response to the input of the logic pattern; and terminating the testing when the toggle coverage is greater than or equal to a predetermined value.

12. The verification method according to claim 11, wherein the toggle coverage testing includes the sub-step of selecting any connection line and monitoring waveforms on the selected connection line in the actual programmable logic device and the simulated programmable logic device.

Brief Patent Description - Full Patent Description - Patent Claims

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Patent Applications in related categories:

20090282375 - Circuit and method using distributed phase change elements for across-chip temperature profiling - Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. ...

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