Phase lock loop with phase interpolation by reference clock and method for the same

This application claims the benefit of U.S. Provisional Application No. 61/015,670, filed on Dec. 21, 2007 and entitled “PHASE LOCK LOOP WITH PHASE INTERPOLATION BY REFERENCE CLOCK AND METHOD FOR THE SAME”, the contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to phase lock loop (PLL), in particular to PLL that employs phase interpolation by reference clock.

2. Description of Related Art

Phase lock loop (PLL) is an important circuit for numerous applications. FIG. 1 depicts a typical PLL 100 for receiving a reference clock and generating an output clock that is phase locked to the reference clock but has an N times higher frequency, where N is an integer. PLL 100 comprises: a phase/frequency detector (PFD) 110 for detecting a phase difference between the reference clock and a feedback clock and generating a phase error signal PE to represent the phase difference; a loop filter (LF) 120 for filtering the phase error signal PE to generate a voltage signal VCON; a voltage-controlled oscillator (VCO) 130 for generating the output clock under the control of the voltage signal VCON; and a divide-by-N circuit 150 for generating the feedback clock by dividing down the output clock by a factor of N. PLL 100 works in a feedback manner, adjusting the voltage signal VCON to force the phase of the feedback clock to align with the reference clock. In a steady state where the feedback clock is well aligned with the reference clock, the phase error signal PE is almost zero and the voltage signal VCON is almost constant.

VCO 130 is a ring oscillator comprising a voltage-controlled delay line (VCDL) 135 connected in a self-feedback topology. VCDL 135 has a delay controlled by the voltage signal VCON. As the delay changes, the oscillating frequency for VCO 130 also changes. In this manner, the oscillating frequency of VCO 130 is controlled by the voltage signal VCON. It has been well known that a ring oscillator is very noisy in general, due to the noise accumulation as the oscillating clock circulates through the VCDL 135 over and over. The noise in the ring oscillator degrades the quality of the output clock of the PLL.

What is needed is an apparatus and a method for reducing the noise of the ring oscillator of the PLL.

In an embodiment, a phase lock loop (PLL) with phase interpolation by a first reference clock is disclosed, the PLL comprising: a phase-interpolation controller for generating a phase-interpolation control signal from an input clock; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a phase interpolation controlled by the phase-interpolation signal and an oscillation condition controlled by the first control signal; and a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer.

In an embodiment, a method of phase locking is disclosed, the method comprising: generating a phase-interpolation control signal from an input clock; detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; filtering the phase error signal to generate a first control signal; generating an output clock under an oscillation condition controlled by the first control signal and a phase interpolation under a control by the phase-interpolation control signal; and dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a functional block diagram of a prior art phase lock loop (PLL).

FIG. 2A shows a functional diagram of a PLL in accordance with the present invention.

FIG. 2B shows an embodiment of a fixed delay circuit and a phase-interpolation controller for the PLL of FIG. 2A.

FIG. 2C shows a timing diagram for the fixed delay circuit and the phase-interpolation controller of FIG. 2B.

FIG. 2D shows an embodiment of a phase interpolator.

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