Array substrate, display device having the same and method of manufacturing the same

This application is a divisional of prior application Ser. No. 11/779,534, filed Jul. 18, 2007, and claims priority from and the benefit of Korean Patent Application No. 2006-67979, filed on Jul. 20, 2006, which are all hereby incorporated by reference for all purposes as if fully set forth herein.

1. Field of the Invention

The present invention relates to an array substrate, a display device including the array substrate, and a method of manufacturing the array substrate. More particularly, the present invention relates to an array substrate capable of decreasing line resistance and the occurrence of line defects, a display device including the array substrate, and a simplified method of manufacturing the array substrate.

2. Discussion of the Background

An array substrate of a flat panel display device includes various lines for transmitting signals, which are formed through thin film deposition processes.

In the flat panel display device, the length of the lines has been increased, and the thickness of the lines has been decreased, thereby increasing the resistance of the lines.

In addition, the lines chemically react with an insulating substrate, an insulating layer, oxygen, etc., so that the resistance of the lines is greatly increased. Therefore, the image display quality is deteriorated.

Furthermore, when a metal layer is etched to form the lines, the etching uniformity of the metal layer may be deteriorated, which may deteriorate the etching profile of the lines.

The present invention provides an array substrate capable of decreasing line resistance and the occurrence of line defects.

The present invention also provides a display device including the above mentioned array substrate.

The present invention also provides a simplified method of manufacturing the array substrate.

The present invention discloses an array substrate including a switching element, a signal transmission line, a passivation layer, and a pixel electrode. The switching element is on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is on the insulating substrate. The conductive line is on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and includes a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is on the insulating substrate and connected to the drain electrode of the switching element through the contact hole.

The present invention also discloses a display device including a switching element, a signal transmitting line, a pixel electrode, a passivation layer, a liquid crystal layer, an opposite electrode, and an opposite insulating substrate. The switching element is on an insulating substrate. The signal transmitting line is connected to the switching element. The signal transmitting line includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is on the insulating substrate. The conductive line is on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The pixel electrode is on the insulating substrate and is connected to a drain electrode of the switching element. The passivation layer covers the switching element and the signal transmission line. The liquid crystal layer is on the passivation layer. The opposite electrode is on the liquid crystal layer and faces the pixel electrode. The opposite insulating substrate is on the opposite electrode and faces the insulating substrate.

The present invention also discloses a method of manufacturing an array substrate that is provided as follows. A barrier layer is formed on an insulating substrate. A gate line and a gate electrode are formed on the barrier layer. The gate line includes copper or copper alloy and the gate electrode is connected to the gate line. Nitride plasma is applied to the gate line and the gate electrode. A gate insulating layer is deposited on the insulating substrate to cover the gate line and the gate electrode. A data line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, and a semiconductor pattern are formed on the gate insulating layer. The source electrode is connected to the data line and the drain electrode is spaced apart from the source electrode. The semiconductor pattern is on the gate electrode between the source electrode and the drain electrode.

The present invention discloses another method of manufacturing an array substrate that is provided as follows. A gate line, a gate electrode, and a gate insulating layer are formed on an insulating substrate. The gate electrode is connected to the gate line. The gate insulating layer covers the gate line and the gate electrode. A semiconductor pattern is formed on the gate insulating layer corresponding to the gate electrode. A data line, a source electrode, and a drain electrode are formed on the gate insulating layer. The data line includes copper or copper alloy. The source electrode is connected to the data line. The drain electrode is spaced apart from the source electrode with respect to the semiconductor pattern. Nitride plasma is applied to the data line, the source electrode, and the drain electrode. A passivation layer is deposited on the gate insulating layer to cover the semiconductor pattern, the data line, the source electrode, and the drain electrode.

The present invention discloses still another method of manufacturing an array substrate that is provided as follows. A first barrier layer, a first conductive layer, and a first copper nitride layer are deposited on an insulating substrate, in sequence. The first conductive layer includes copper or copper alloy. The first barrier layer, the first conductive layer, and the first copper nitride layer are patterned to form a gate line and a gate electrode connected to the gate line. A gate insulating layer is deposited on the insulating substrate to cover the gate line and the gate electrode. A data line, a source electrode, a drain electrode, and a semiconductor pattern are formed on the gate insulating layer. The source electrode is connected to the data line and the drain electrode is spaced apart from the source electrode. The semiconductor pattern is on the gate electrode between the source electrode and the drain electrode.

The present invention discloses yet another method of manufacturing an array substrate that is provided as follows. A barrier layer is formed on an insulating substrate. A gate line and a gate electrode are formed on the barrier layer. The gate line includes copper or copper alloy and the gate electrode is connected to the gate line. Hydrogen plasma is applied to the gate line and the gate electrode. A first gas mixture is injected into a chamber to form a first gate insulating layer on the insulating substrate. The first gas mixture includes silane gas, nitrogen gas, and ammonia gas. The amount of silane gas in the first gas mixture is no more than about 6.43% by volume. A second gas mixture is injected into the chamber to form a second gate insulating layer on the insulating substrate. The second gas mixture includes silane gas, nitrogen gas, and ammonia gas. The amount of silane gas in the second gas mixture is no less than about 6.43% by volume. A third gas mixture is injected into the chamber to form a third gate insulating layer on the insulating substrate. The third gas mixture includes silane gas, nitrogen gas, and ammonia gas. The amount of silane gas in the third gas mixture is no more than about 6.43% by volume. A data line, a source electrode, a drain electrode, and a semiconductor pattern are formed on the third gate insulating layer. The source electrode is connected to the data line and the drain electrode is spaced apart from the source electrode. The semiconductor pattern is on the gate electrode between the source electrode and the drain electrode.

It is to be understood that both the foregoing and general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.