Pll circuit

The present application claims priority from Japanese Patent Application No. JP 2007-332026 filed on Dec. 25, 2007, the content of which is hereby incorporated by reference into this application.

The present invention relates to a PLL (Phase Locked Loop) circuit, in particular, to technique effectively applied to a hybrid control type PLL circuit including a voltage controlled oscillator controlled by both of a digital control signal and an analog control signal.

As for technique examined by the inventor, there is the following technique in the PLL circuit, for example.

In Japanese Patent Application Laid-Open Publication No. 2001-257567 (Patent Document 1), a circuit configuration of a voltage controlled oscillator enabling generation of a clock signal having small jitter even when a power source voltage fluctuates, in the PLL circuit including a phase comparator, a frequency comparator and a voltage controlled oscillator is shown, for example. Specifically, a configuration in which, with respect to a configuration including a ring oscillator and capacitance mutually connected in parallel and a MOS transistor controlling an oscillation frequency by controlling a power source voltage (current) thereof, a second means for controlling the oscillation frequency according to a phase comparison result is provided. This second means is realized by capacitance capable of switching connection/disconnection with respect to the ring oscillator, and according to the phase comparison result, when the capacitance is connected, the oscillation frequency lowers with increase of a load and when the capacitance is disconnected, the opposite operation is performed.

And, in Japanese Patent Application Laid-Open Publication No. 2005-252723 (Patent Document 2), a PLL circuit having a configuration in which the comparison result of the frequency comparator is reflected to a VCO (Voltage Controlled Oscillator) through a processing by an integration circuit, a comparator and a gain adjustment circuit is shown. This frequency comparator compares and determines high and low of the frequency by observing change of a phase of an input clock using three phase periods obtained from three phase clocks from the VCO as a reference. By reflecting the result of such frequency comparator to the VCO through various processes described above, even if false detection of the frequency comparator occurs, influence thereof can be reduced.

Note that, in the technique of the PLL circuit described above, the following is found by examination by the inventor.

For example, the PLL circuit shown in Patent Document 1 has a configuration of hybrid control controlling the oscillation frequency of the voltage controlled oscillator by digital control and analog control. In the digital control, the switch of connection/disconnection of the capacitance serving as the second means is performed based on a digital signal which is the phase comparison result. On the other hand, in the analog control, a gate voltage of the abovementioned MOS transistor controlling the oscillation frequency is controlled in an analog manner by an output of a charge pump circuit, and charge/discharge of this charge pump circuit is controlled based on the phase comparison result and the frequency comparison result.

FIG. 14 is a circuit diagram showing a schematic configuration of a voltage controlled oscillator circuit included in the PLL circuit examined as a premise of the present invention.

The voltage controlled oscillator circuit VCO shown in FIG. 14 reflects characteristics of the voltage controlled oscillator circuit shown in Patent Document 1, and is composed of a ring oscillator circuit OSC, capacitances C1 to C3, an NMOS transistor T1, PMOS transistors T2, T3, a resistor R1 and the like. The ring oscillator circuit OSC is provided between a high potential side power source node Vdd and a second low potential side power source node Vss2. The NMOS transistor T1 is provided between the second low potential side power source node Vss2 and a first low potential side power source node Vss, and by a gate voltage thereof, a supplying current to the ring oscillator circuit OSC is controlled, and as a result, the oscillation frequency of the ring oscillator circuit OSC is controlled through control of a voltage of the second low potential side power source node Vss2.

The capacitance C3, the PMOS transistor T2 and the PMOS transistor T3 are connected in series in order to the high potential side power source node Vdd, and an end of the PMOS transistor T3 is connected to an internal node of the ring oscillator circuit OSC. ON/OFF of the PMOS transistor T2 is controlled by a digital control signal S_DG. When the PMOS transistor T2 is controlled to ON, the capacitance C3 is added to the ring oscillator circuit OSC. Therefore, by controlling the PMOS transistor T2 to OFF, the oscillation frequency can be set to relatively high, and by controlling the same to ON, the oscillation frequency can be set to relatively low. Note that, a gate of the PMOS transistor T3 is connected to the second low potential side power source node Vss2, and is normally kept at an ON state. This PMOS transistor T3 is for preventing coupling noise involved in ON/OFF of the digital control signal S_DG from directly influencing the internal node of the ring oscillator circuit OSC, and may be omitted in some cases. Thus, by using digital control by the digital control signal S_DG, microscopic change of the oscillation frequency caused by thermal noise and the like of the ring oscillator circuit OSC can be corrected all at once by a single control.

On the other hand, to a gate of the NMOS transistor T1, an analog control signal S_AG is applied via a low pass filter composed of a resistor R1 and capacitance C2. By using the digital control described above in combination, high speed operation is not required for analog control by the analog control signal S_AG. Therefore, the analog control signal S_AG can be connected via the low pass filter, and furthermore, capacitance C1 can be provided between the high potential side power source node Vdd and the second low potential side power source node Vss2. Accordingly, fluctuation of an analog control voltage and fluctuation of a power source voltage applied to the ring oscillator circuit OSC caused by sudden power source noise and the like can be suppressed as much as possible, and therefore, fluctuation of the oscillation frequency caused by them can be suppressed.

Here, if the configuration of Patent Document 1 is employed, the digital control signal S_DG alternately transits between a high level and a low level reflecting the phase comparison result in a steady state, for example, and according to this, connection/disconnection of the capacitance C3 is alternately switched. In this state, frequency adjustment by the analog control converges and frequency fluctuation of a control width involved in the digital control is applied upward and downward around the converged frequency. The control width of the frequency involved in the switching of the capacitance C3 in the digital control is required to ensure a size of an extent correcting high speed noise by thermal noise of the ring oscillator circuit OSC. It is preferable that the size of the control width by the digital control is the necessity minimum because it becomes a jitter component in the steady state.

On the other hand, it is preferable that the minimum control width of the frequency by the analog control is about ⅕ to 1/10 or lower of the control width by the digital control, for example. Thereby, when change equivalent to the control width occurs in the analog control, the control widths of the digital control appropriately overlaps before and after thereof, and suitable frequency adjustment can be realized. Therefore, in order to reduce the control width of the digital control as described above, the control width of the analog control has to be reduced as much as that.

However, in order to reduce the control width of the analog control, a charge movement amount per one charge and discharge by the charge pump circuit has to be reduced. To realize this, elements such as transistor configuring the charge pump circuit must be made small. However, there is a limit to the minimum size of the element which can be created in semiconductor technology used, and the charge movement amount per one time of the charge pump circuit configured with the element of such size is the limit of the reduction. Therefore, a limit of reduction of the control width of the digital control and a limit of reduction of the phase jitter are determined by this.

An object of the present invention is to remove the limit of the minimum control width of a frequency and to enable further reduction of phase jitter, in the PLL circuit.

The present invention is proposed in view of the above, and the above and other objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

The typical ones of the embodiments disclosed in this application will be briefly described as follows.

That is, the PLL circuit of the typical embodiment includes a means for detecting whether the steady state has been reached and performs partially different operation between a case in which the steady state has been reached and a case in which the steady state has not been reached.

For example, if the steady state has not been reached, the charge movement amount per one cycle on average is reduced by lowering frequencies of charge and discharge by the charge pump circuit. If the steady state has been reached, the frequencies of charge and discharge cannot be lowered in order to keep the state. Instead, however, since charge and discharge are performed in a substantially alternating manner if the steady state has been reached, the charge and the discharge cancel each other and it becomes substantially zero on average.