Apparatus and method for clock signal synchronization in jtag testing in systems having selectable modules processing data signals at different rates

1. Field of the Invention

This invention relates to the application of a system clock to a plurality of selectable modules that process the clock signals at different rates. In particular, the modules process test and debug signals, such as JTAG signals, at different clock rates.

2. Background of the Invention

In certain processing units, different modules can process input signals at different clock rates. For example, modules of certain ARM Corporation processing units process test and debug signals at different rates depending on the module. In the JTAG test and debug format, not only is a clock (CLK) signal required, but a return clock (RCKL) signal must be present.

Referring to FIG. 1, a system having a plurality of modules processing data groups at different rates is illustrated. The processing system includes modules 1-N. Each module has a (system) CLK signal applied to an input terminal thereof. Each module processes data at a rate that is module-dependent. When the processing of the data is complete, the modules generate RCKL(l) through RCKL(N) signals. In FIG. 1, the application of test data in TDI(1) through test data in TDI(N) to the modules is illustrated. After processing, the test data out TDO(1) through test data out TDO(N) is retrieved from the modules. In the important JTAG example, the TDI(1) through the TDI(N) are applied, by means of a chain configuration, to the modules and the TDO(1) and TDO(N) are retrieved series format from the modules through a chain configuration. Consequently, it is necessary that the system clock signal be consistent with any of the RCLK(h) signals. Expressed in another manner, the TDI(k) are entered in the module, processed during a period of time determined by the design of the module, and retrieved from the modules for analysis.

As will be clear, either through failure of the system clock or as a result of variations in the time to process the data signals entered into each module, a timing error will occur.

In a typical test procedure, not all of the modules of the processing unit may be the subject of a particular test procedure. To include those modules might compromise the test procedure or reduce the speed with which the test and debug procedure can be performed.

It is therefore a feature of the apparatus and associated method to perform a test and debug procedure on selected modules of a processing system. It is yet another feature of the apparatus and associated method to determine when a return clock signal is not consistent with system clock signal during a test and debug procedure of processing unit having selectable modules. It is a more particular feature of the apparatus and associated method to generate return clock negative edge and positive edge signals for use in generating a composite RCL signal. It is yet another particular feature of the apparatus and associated method to apply RCLK_NE and RCLK_PE signals from selected modules to an adder circuit, the RCLK_NE and RCLK_PE signals being synchronized with the module RCLK signal. It is still a further feature of the present invention to apply RCKL_NE and RCLK_PE signals continuously to the adder unit for the deselected modules. It is yet another particular feature of the present invention to provide a seamless transition between the selection and the deselection of a module.

The aforementioned and other features are accomplished, according to the present invention, by providing each module with a selection unit. In response to a SELECT signal, the selection unit will provide a RCLK_PE (RCLK POSITIVE EDGE) signal and a RCLK_NE (RCLK NEGATIVE CLOCK) signal to an adder circuit, the RCLK_PE signals and the RCLK_NE signals being synchronized with the RCLK signal from the associated module. The RCLK_NE and RCLK_PE signals from the selected modules are combined to form a composite RCLK signal. For those modules for which the SELECTION signal is not applied, the RCLK_NE and RCLK_PE signals are continually applied to the adder unit. Because the RCLK_NE and the RCLK_PE signals from the non-selected modules are continuously applied to the adder unit, these signals do not participate in the generation of the composite RCLK signal, only the selected modules contribute to the formation of the composite RCLK signal. Therefore, only the selected modules contribute to the composite RCLK signal. The composite RCLK signal is compared with the CLK signal to identify timing problems in the (selected) modules.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a system having a plurality of modules processing data signals at different rates according to the prior art.

FIG. 2 is a block diagram for generating a composite RCLK signal for a system having a plurality of modules processing data signals at different rates according to the present invention.

FIG. 3 illustrates the waveforms generated by the circuit of FIG. 2.

FIG. 4 is a circuit diagram showing an implementation of an adder unit circuits for generating a RCLK signal suitable for use in FIG. 2.

FIG. 5 is a block diagram of a test and debug system with selectable modules according to the present invention.

FIG. 6 is a schematic diagram of the selection circuit associated with each module according to the present invention.

FIG. 7 is a schematic diagram of the adder unit when POSITIVE EDGE and NEGATIVE EDGE signals re applied to the adder unit according to the present invention.

FIG. 8 illustrates the waveforms in the selection unit of FIG. 6 when the SELECT signal is applied according to the present invention.

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Miscellaneous active electrical nonlinear devices, circuits, and systems

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