Apparatus and method for clock signal synchronization in jtag testing in systems having modules processing clock signals at different rates

1. Field of the Invention

This invention relates to the application of a system clock to a plurality of modules that process the clock signals at different rates. In particular, the modules process test and debug signals, such as JTAG signals, at different clock rates.

2. Background of the Invention

In certain processing units, different modules can process input signals a different clock rates. For example, modules of the ARM Corporation processing units process test and debug signals at different rates. In the JTAG test and debug format, not only is a clock (CLK) signal required, but a return clock (RCKL) signal must be present.

Referring to FIG. 1, the problem engendered by the variable processing rate modules is illustrated. The processing system under test includes modules 1-N. Each module has a (system) CLK signal applied to an input terminal thereof. Each module processes data according to its own internal clock. When the processing of the data is complete, the modules generate RCKL(1) through RCKL(N) signals. In FIG. 1, the application of rest data in TDI(1) through test data out TDI(N) to the modules is illustrated. After processing, the test data out TDO(1) through test data out TDO(N) is retrieved from the modules. In the important JTAG example, the TDI(1) through the TDI(N) are applied, in a series data format, to the modules and the TDO(1) and TDO(N) are retrieved in series format from the modules. Consequently, it is necessary the system clock signal not conflict with any of the RCLK(h) signals or the serial retrieval of the data signals can be compromised. Expressed in another manner, the TDI(k) are entered in the module, processed during the system clock interval and the TDO(k) retrieved from the modules for analysis.

As will be clear, either through failure of the system clock or as a result of variations in the time to process the data signals entered into each module, a timing error can occur and compromise the retrieved data.

It is therefore a feature of the apparatus and associated method to determine when a timing error has occurred in a group of modules that can process portions of a data stream at different rates. It would be yet another feature of the apparatus and associated method to determine when all the return clock signals from the a plurality of modules have a first logic state. It is yet another feature of the present invention to determine when all the module return clock signals have a second logic state. It is yet another feature of the present invention to determine when the return clock signals are inconsistent with the system clock signals. It is a more particular feature of the apparatus and associated method to provide an ERROR signal in the event of potential data corruption in a JTAG test and debug procedure. It is yet a further particular feature of the apparatus and associated to reset the apparatus after the generation of an error signal in response to an externally applied initiation signal.

The aforementioned and other features are accomplished, according to the present invention, by a first circuit that provides a signal when all of the RCK signals from the modules are in a first state and a second circuit that provides a second signal when the RCLK signals are in a second state. The output signals from the first and second circuits are latched until the opposite state signal is generated. The latched signal is compared to the system clock signal, the system clock being the system clock signal for all of the modules. When the comparison is positive, activity of the modules is continued. When the comparison is negative, an ERROR signal is generated and the results of the previous activity of the modules are discarded. In one implementation, when the ERROR signal is generated, an external signal can initialize the apparatus.