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06/18/09 - USPTO Class 716 | 1 views | #20090158231 | Prev - Next | About this Page

Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

Title: Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20090158231, Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same.

What is claimed is:

1. A design structure embodied in a machine readable medium used in a design process of an integrated circuit, the design structure of said integrated circuit comprising: a first wire of a first level of wiring tracks; a second wire of a second level of wiring tracks, said second level being adjacent said first level; a first via connecting said first and second wires at a first location of said second wire; a third wire of a third level of wiring tracks, said third level being adjacent said second level; a second via connecting said second and third wires at said first location, said second via being substantially axially aligned with said first via; a fourth wire located a first distance from said second wire in said second level; a third via connecting said third and fourth wires at a second location of said fourth wire; and a fourth via connecting said first and fourth wires at said second location, said fourth via being substantially axially aligned with said third via; wherein said second, third, and fourth vias, and said third and fourth wires form a path between said first and second wires redundant to said first via.

2. A design structure of claim 1, wherein the design structure comprises a netlist, which describes the circuit.

3. A design structure of claim 1, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

4. A design structure of claim 1, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications

5. A design structure embodied in a machine readable medium used in a design process of an integrated circuit, the design structure of said integrated circuit comprising: a first wire of a first level of wiring tracks; a second wire of a second level of wiring tracks, said second level being adjacent said first level; a third wire of a third level of wiring tracks, said third level being adjacent said second level, said third wire being aligned vertically and running substantially parallel with said first wire; a first via connecting said first and second wires; a second via connecting said third wire to said second wire; a fourth wire located a first distance from said second wire in said second level; a third via connecting said third wire and said fourth wire; a fourth via connecting said first wire to said fourth wire, wherein said second, third, and fourth vias provide a path between said first and second wires that is redundant to said first via.

Brief Patent Description - Full Patent Description - Patent Claims

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Industry Class:
Data processing: design and analysis of circuit or semiconductor mask

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