Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

The present invention generally relates to the field of integrated circuit physical design. In particular, the present invention is directed to a design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same.

As the physical dimensions of very large scale integrated circuits (VLSI) continue to shrink, it has become increasingly difficult to manufacture such integrated circuits in a reliable fashion. The sensitivity of a VLSI design to random defects increases as feature widths and spacing between features grow smaller. In addition, the presence of single vias (i.e., inter-layer connectors through a single via) is particularly undesirable. From the perspective of random-defect yield, a single via is especially likely to cause a chip failure because a spot-defect landing on a single via will create an open circuit. From the perspective of systematic yield, if vias are difficult to manufacture in a given process, a poorly created single via can cause a circuit open or a highly resistive connection, which can cause a circuit to fail. New manufacturing processes are particularly sensitive to yield problems that are related to the formation of vias. An example of a single via structure is shown with reference to FIGS. 1A and 1B.

For these reasons, a need exists for improved structures for implementing redundant vias in an integrated circuit physical design process, in order to reduce the complexity of the manufacturing process, maintain high wiring density, and maximize manufacturing yield.

In one implementation, a design structure embodied in a machine readable medium used in a design process of an integrated circuit is provided. The design structure of the integrated circuit includes a first wire of a first level of wiring tracks; a second wire of a second level of wiring tracks, the second level being adjacent the first level; a first via connecting the first and second wires at a first location of the second wire; a third wire of a third level of wiring tracks, the third level being adjacent the second level; a second via connecting the second and third wires at the first location, the second via being substantially axially aligned with the first via; a fourth wire located a first distance from the second wire in the second level; a third via connecting the third and fourth wires at a second location of the fourth wire; and a fourth via connecting the first and fourth wires at the second location, the fourth via being substantially axially aligned with the third via; wherein the second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

In another implementation, a design structure embodied in a machine readable medium used in a design process of an integrated circuit is provided. The design structure of the integrated circuit includes a first wire of a first level of wiring tracks; a second wire of a second level of wiring tracks, the second level being adjacent the first level; a third wire of a third level of wiring tracks, the third level being adjacent the second level, the third wire being aligned vertically and running substantially parallel with the first wire; a first via connecting the first and second wires; a second via connecting the third wire to the second wire; a fourth wire located a first distance from the second wire in the second level; a third via connecting the third wire and the fourth wire; a fourth via connecting the first wire to the fourth wire, wherein the second, third, and fourth vias provide a path between the first and second wires that is redundant to the first via.

BRIEF DESCRIPTION OF THE DRAWINGS

For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention. However, it should be understood that the present invention is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein:

FIG. 1A illustrates a top view of a single via structure, which is a structure that is commonly found in integrated circuit design;

FIG. 1B illustrates a cross-sectional view of the single via structure, taken along line AA of FIG. 1A;

FIG. 2A illustrates a top view of a redundant via structure, which is a structure that is found in integrated circuit design;

FIG. 2B illustrates a cross-sectional view of the redundant via structure, taken along line AA of FIG. 2A;

FIG. 3A illustrates a top view of a single via structure, which is a structure that is found in integrated circuit design;

FIG. 3B illustrates a cross-sectional view of the single via structure, taken along line AA of FIG. 3A;

FIG. 4A illustrates a top view of a redundant micro-loop structure, in accordance with the disclosure;

FIG. 4B illustrates a cross-sectional view of the redundant micro-loop structure, taken along line AA of FIG. 4A;

FIG. 5 illustrates a method of forming redundant micro-loop structures in an integrated circuit physical design process, in accordance with the disclosure;

FIG. 6 illustrates one example of a general purpose computing environment; and

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