Method and system for calculating high frequency limit capacitance and inductance for coplanar on-chip structure

This application is a continuation of U.S. Ser. No. 11/948,761, filed Nov. 30, 2007, the entire contents of which are incorporated herein by reference.

The present invention is related to commonly-owned, co-pending United States Patent Application No. US 2006/0286691 entitled “Capacitance Modeling”, the entire contents and disclosure of which is incorporated by reference as if fully set forth herein.

1. Field of the Invention The present invention relates generally to the high speed electronic devices, and more particularly, to a method and system for calculating the high frequency capacitance and high frequency inductance limits (two separate, but connected problems) in two-dimensional (2D) on-chip interconnect structures.

2. Description of the Prior Art

High-speed electronic devices on silicon chips successfully operate today at frequencies up to 100 GHz, considering technologies such as SiGe and SOI. Coplanar transmission lines turn to be important on-chip interconnects for such devices. In order to have a model for coplanar structures on silicon substrates, the following low frequency and the high frequency limit values of the following electrical parameters have to be calculated: static capacitance C₀, infinite (high frequency limit) capacitance C_∞, low frequency inductance L₀ and infinite (high frequency limit) inductance L_∞. In addition to this, the low and high frequency values of the resistance and shunt conductance have to be calculated as well. Prior art techniques for capacitance and inductance calculation were developed mostly for calculation of the low frequency (static) capacitance C₀ and low frequency inductance L₀, since prior art applications were mainly for lower frequencies, where modeling of the static values is sufficient. The high frequency limit capacitance becomes important for transmission lines, or any metal conductor structures right above the silicon substrate at high frequencies (several GHz and higher) in which the silicon behaves as a dielectric material rather than like a metal. As is apparent from prior art teachings described in commonly-owned, co-pending United States Patent Publication No. 2005/0262458 (Atty. Docket No. IL9200413US1 filed on May 6, 2005 entitled “Modeling Capacitance of On-chip Coplanar Transmission Lines Over the Silicon Substrate”, existing closed-form expressions for the coplanar transmission line high frequency limit capacitance are quite complex, and their accuracy is not always sufficient. Numerical calculations are time and memory consuming and may not be stable. Moreover, the existing prior art solutions requires usage of an EM solver as described in the aforementioned United States Patent Publication No 2005/0262458. EM solver calculations are time consuming and may have convergence problems.

In commonly-owned, co-pending United States Patent Publication No. 2006/0286691 there was described methods for calculating the static capacitance. In the low frequency limit of US20060286691, the silicon is treated as a metal.

In commonly-owned, co-pending United States Patent Publication No. 2005/0262458 there is described a methodology that addresses the same problem of calculating the high frequency limit capacitance but using a very different imaging method, which is not based on a field lines approach. The method described in US 2005/0262458 is very complex. Moreover, none of these cited prior art references teach or suggest a method for the calculation of the high frequency limit inductance.

What would be highly desirable is to provide field based expressions for deriving and calculating high frequency capacitance C_∞ and inductance L_∞ of a coplanar transmission line structure over the silicon substrate, which are very compact and have the desired accuracy for many applications.

It is an object of the present invention to provide field based expressions for deriving and calculating high frequency capacitance C_∞ and inductance L_∞ of coplanar transmission line structures over a silicon substrate.

It is a further object of the present invention to provide field based expressions for deriving and calculating high frequency capacitance C_∞ and inductance L_∞ of coplanar transmission line (T-line) structures over a silicon substrate wherein the high frequency limit capacitance is calculated for: a single coplanar T-line structure over a substrate, or a coupled coplanar T line over the silicon substrate.

It is a further object of the present invention to provide field based expressions for calculating a high frequency limit inductance for a case where no silicon substrate exists.

Thus, according to one aspect of the invention, there is provided a computer program product for modeling the high frequency limit capacitance of an on-chip interconnect structure disposed above a silicon substrate having a dielectric material layer, the interconnect structure including a conductor structure and a proximate side shield structure, the computer program product comprising a computer usable medium having computer usable program code embodied therewith, the computer usable program code comprising:

a) computer usable program code configured for estimating a pattern of electric field lines within the silicon substrate structure and within the dielectric material layer, the estimated pattern of electric field lines comprising a curved field lines portion and straight lines portion between the conductor structure and a proximate side shield structure;

b) computer usable program code configured for providing parameters to the computer device for characterizing the silicon substrate at the high frequency as a non-conductive dielectric material, the estimated pattern of electric field lines in the silicon substrate behaving according to the non-conductive, dielectric material characterization, one parameter including an effective dielectric constant C used for calculating partial capacitance expressions of the interconnect structure, the effective dielectric constant ∈ calculated according to:

α/∈₁+β/∈₂==(α+β)/∈