Scaffold-organized metal, alloy, semiconductor and/or magnetic clusters and electronic devices made using such clusters

This application is a continuation of U.S. patent application Ser. No. 10/816,603, filed Apr. 2, 2004, which is a continuation of pending U.S. patent application Ser. No. 10/013,334, filed Nov. 5, 2001, which is a continuation of U.S. patent application Ser. No. 09/085,390, filed May 27, 1998, now abandoned, which claims the benefit of the earlier filing date of U.S. Provisional Patent Application No. 60/047,804, filed May 27, 1997, now abandoned. Each of these prior patent applications is incorporated herein by reference.

This invention was made with government support under contract numbers N00014-93-0618 and N00014-93-1-1120 awarded by the Department of Defense, Office of Navel Research, and under Grant No. DMR-9705343 awarded by the National Science Foundation. The government has certain rights in the invention.

This invention concerns a method for forming organized arrays of metal, alloy, semiconductor and/or magnetic clusters for use in the manufacture of electronic devices, such as high density memory storage and nanoelectronic devices.

Fundamentally new technologies are required to continue increasing device integration density and speed. Conventional metal-oxide semiconductor-field-effect transistors soon will reach fundamental density and speed limits as a result of quantum mechanical tunneling. In order to scale electronic device sizes down to nanometer dimensions, systems containing increasingly fewer numbers of particles must be considered.

The ultimate limit is a system in which the transfer of a single charge quanta corresponds to information transfer or some type of logical operation. Such single electron systems are presently the focus of intense research activity. See, for example, Single Charge Tunneling, Coulomb Blockade Phenomena in Nanostructures, edited by H. Grabert and M. H. Devoret, NATO ASI Series B: Physics Vol. 294 (1992). These systems have potential application to nanoelectronic circuits that have integration densities far exceeding those of present day semiconductor technology. See, Quantum Transport in Ultrasmall Devices, edited by D. K. Ferry, H. L. Grubin, C. Jacoboni, and A. Jauho, NATO ASI Series B: Physics Vol. 342 (1995).

Single electron transistors based on the concept of Coulomb blockade are one proposed technology for realizing ultra-dense circuits. K. K. Likharev\'s Single Electron Transistors: Electrostatic Analogs of the DC SQUIDS,” IEEE Trans. Magn. 23:1142 (1987); and IBM J. Res. Dev. 32:144 (1988). Coulomb blockade is the suppression of single electron tunneling into metallic or semiconductor islands. In order to achieve Coulomb blockade, the charging energy of an island must greatly exceed the thermal energy. To reduce quantum fluctuations the tunneling resistance to the island should be greater than the resistance quantum h/e². Coulomb blockade itself may be the basis of conventional logic elements, such as inverters. Id.

Equally promising is the fact that the Coulomb blockade effect can be used to pump charges one-by-one through a chain of dots to realize a frequency-controlled current source in which the current is exactly equal to I=ef, where f is the clocking frequency. See, L. J. Geerligs et al.\'s Frequency-locked Turnstile Device for Single Electrons, Phys. Rev. Lett., 64:2691 (1990); and H. Pothier et al.\'s Single-Electron Pump Based on Charging Effects, Europhys. Lett. 17:249 (1992). Such turnstile devices are of fundamental interest as highly accurate current standards.

The clocking of charge through an array is also one model of information storage. It is possible that computation may be based on switching of currents rather than charge which, due to the extreme accuracy of single electron current sources, may be more robust towards unwanted fluctuations than single electron transistor-based circuits.

One of the most promising technologies for realizing terabyte memories is founded on the principle of the Coulomb blockade. Yano et al. have demonstrated room temperature operation of single electron devices based on silicon nanocrystals embedded in SiO₂. K. Yano et al.\'s Room-Temperature Single Electron Memory, IEEE Trans. Electron. Devices, 41:1628 (1994); and K. Yano et al.\'s Transport Characteristics of Polycrystalline-Silicon Wire Influenced by Single Electron Charging at Room Temperature, Appl. Phys. Lett., 67:828 (1995). Recently, a fully integrated 8×8 memory array using this technology has been reported. K. Yano et al.\'s Single-Electron-Memory Integrated Circuit for Giga-to-Tera Bit Storage, IEEE International Solid State Circuits Conference, p. 266-267 (1996).

Microelectronic devices based on the principle of Coulomb blockade have been proposed as a new approach to realizing electronic circuits or memory densities that go beyond the predicted scaling limit for present day semiconductor technology. While the operation of Coulomb blockade devices has been demonstrated, most operate only at greatly reduced temperatures and require sophisticated nanofabrication procedures. The size scales necessary for Coulomb blockade effects at such relatively elevated temperatures of about room temperature impose limits on the number, uniformity and connectivity of quantum dots. As a result, alternative methodologies of nanofabrication need to be investigated and developed.

The present invention provides a new process for making arrays comprising metal, alloy, semiconductor and/or magnetic clusters. An “array” can be any arrangement of plural such clusters that is useful for forming electronic devices. Two primary examples of arrays are (1) electronic circuits, and (2) arrangements of computer memory elements, both of which can be in one or several planes.

“Clusters” as used herein refers to more than one, and typically three or more, metal, alloy, semiconductor or magnetic atoms coupled to one another by metal-type bonds. Clusters are intermediate in size between single atoms and colloidal materials. Clusters made in accordance with the present invention also are referred to herein as “nanoclusters.” This indicates that the radius of each such cluster preferably is from about 0.7 to about 1.0 nm. A primary goal of the present invention is to provide electronic devices that operate at or about room temperature. This is possible if the cluster size is made small enough to meet Coulomb blockade charging energy requirements at room temperature. While cluster size itself is not dispositive of whether the clusters are useful for forming devices operable at or about room temperature, cluster size is nonetheless quite important. It currently is believed that clusters having radiuses much larger than the maximum value stated above likely will not be useful for forming electronic devices that operate at or about room temperature.

The metal, alloy, semiconductor and/or magnetic clusters are bonded to “scaffolds” to organize the clusters into arrays. “Scaffolds” are any molecules that can be placed on a substrate in predetermined patterns, such as linear bridges between electrodes, and to which clusters can be bonded to provide organized cluster arrays. Without limitation, a preferred group of scaffolds comprise biomolecules, such as polynucleotides, polypeptides, and mixtures thereof. Polypeptides are currently preferred molecules for forming scaffolds, and polypeptides capable of forming a helices are particularly preferred scaffold-forming molecules.

One embodiment of a method for forming arrays of metal, alloy, semiconductor and/or magnetic clusters first involves placing the scaffold on a substrate, most likely in a predetermined pattern. Arrays are formed by contacting the scaffold with plural, monodispersed (clusters of substantially the same size) ligand-stabilized metal, alloy, semiconductor and/or magnetic clusters. If the clusters are metal clusters, then the metal preferably is selected from the group consisting of Ag, Au, Pt, Pd and mixtures thereof. A currently preferred metal is gold, and a currently preferred metal cluster is Au₅₅.