Memory cell circuit, memory device, motion vector detector, and motion compensation predictive encoder

This invention relates to a memory cell circuit, a memory device, a motion vector detector, and a motion compensation predictive encoder.

On sequential data, simultaneous processing of data in a relatively small domain is often preferred. For example, in processing image data, data to be processed on target pixel is generated from multiple items of the data of the target pixel and its peripheral pixels. In motion estimation (ME) of a motion vector by block-matching, based on given pixel data within a given pixel block having a predetermined dimension on a location in a preceding frame, an estimation is made as to which of pixel data within a pixel block having the same dimension as the above pixel block in the subsequent frame is the closest to the above given pixel data. The displacement between positions of the two-pixel blocks is defined to be a motion vector.

Here, the items of the pixel data within the above pixel blocks are simultaneously read out of a memory storing the image data, and calculation of differences between the corresponding items of pixel data is also simultaneously performed for each of the pixels. Such data processing leads to a use of a natural and hence comprehensive processing system or algorithm.

Conventionally, however, a general-purpose memory such as a synchronous DRAM is used as a memory storing the image data, and thus, the pixel data is sequentially read out of the general-purpose memory with a high transfer rate and temporarily accumulated in a register to form a necessary tap or a necessary pixel block. In this case, it is inevitable to generate waiting time when all the items of data are accumulated, which has been of a hindrance to a high-speed and efficient processing of image data.

In a conventional data processing of a motion picture, a motion vector is used that represents a motion direction and magnitude of an object in the images that are displaced in time. Such a motion vector is used in motion compensation predictive encoding of an image for high-efficiency coding.

As a motion magnitude determination method for determining this image, Japanese Patent Publication H7-222157 discloses a method for forming multiple hierarchical classes of image data having different resolutions from the input image data, and determining motion vector of a set position of input image using the multiple hierarchical classes of image data, to reduce an amount of operation.

In this motion vector determination method, the input image data (image data of hierarchical class 1) is first averaged according to mean-value hierarchizing such as averaging and low-pass filtering to produce the image data having a reduced number of pixels (image data of hierarchical class 2). Next, a rough motion vector is determined in the image data of hierarchical class 2, and then a fine motion vector is determined in the image data of hierarchical class 1 based on the rough motion vector, thereby permitting the determination of a motion vector with a reduced amount of calculation.

It would be apparent that the number of hierarchical classes is not limited to two as in the example shown above. A motion vector may be determined as the above cases by repeating the mean-value hierarchizing in sequence to produce further hierarchical classes 3 and 4 of image data having further reduced numbers of pixels.

In this case, if the same memory unit stores image data belonging to the respective hierarchical classes when read and write of the image data of the respective hierarchical classes can be made independently, this has an increased efficiency.

It is, therefore, an object of the invention to provide a memory device and the like capable of simultaneously accessing multiple items of pixel data constituting a pixel block having an arbitrary configuration such as a rectangle and a cross, and of easily changing a position of the pixel block, thereby facilitating the processing thereof at high-speed and with efficiency.

It is another object of the invention to provide a motion vector detector capable of increasing efficiency for detecting a motion vector using respective hierarchical classes of image data by allowing different hierarchical classes of image data to be independently written to and read out of a memory unit, and to provide a memory device for use in such motion vector detector, and to provide a memory cell circuit for use in such memory device.

A memory device in accordance with the invention is a memory device comprising one or more memory blocks, wherein each memory block includes multiple memory cells arranged in a matrix form, and multiple selection lines for selecting memory cell column extending in one direction of the matrix, each line corresponding to the memory cell column, wherein an area of the multiple memory cells arranged in a matrix form has multiple divisional domains divided in the one direction of the matrix, wherein each of the multiple selection lines has multiple divisional selection lines divided corresponding to the multiple divisional domains, and wherein the memory block further includes switching mechanism for switching the divisional selection lines that are simultaneously activated in the associated divisional domains.

An inventive motion vector detector in accordance with the invention for detecting a motion vector from a reference frame and a search frame that are displaced in time, comprises a first memory unit for storing multiple items of pixel data constituting the reference frame, a second memory unit for storing multiple items of pixel data constituting the search frame, an operation unit for receiving pixel data of the reference block read out of the first memory unit and pixel data of multiple candidate blocks in the search block, the pixel data of multiple candidate blocks being associated with the reference block and read out of the second memory unit, and for calculating differences between the pixel data in the multiple candidate blocks and the pixel data of the reference block every corresponding item of pixel data, in relation to the respective multiple candidate blocks, and a motion vector detection unit for detecting a motion vector associated with the reference block based on the differences calculated for each of the items of pixel data in relation to the respective multiple candidate blocks operated in the operation unit, wherein each of the first and second memory units comprises one or more semiconductor memory block, wherein the semiconductor memory block has multiple bit lines, multiple word lines perpendicularly crossing the multiple bit lines, and multiple memory cells arranged in a matrix form and connected with the bit lines and the word lines, wherein an area of the multiple memory cells arranged in the matrix form has multiple divisional domains divided in a direction along the word line, wherein each of the multiple selection lines has multiple divisional word lines divided corresponding to the multiple divisional domains, and wherein the semiconductor memory block further has switching mechanism for switching the divisional word lines that are simultaneously activated in the divisional domains.

Further, another motion vector detector in accordance with the invention for detecting a motion vector from a reference frame and a search frame that are displaced in time, comprises a first memory unit for storing multiple items of pixel data constituting the reference frame, a second memory unit for receiving pixel data of the reference block read out of the first memory unit as reference data and for calculating differences between the pixel data in multiple candidate blocks in the search area associated with the reference block and the pixel data of the reference block every corresponding item of pixel data, in relation to the respective multiple candidate blocks, and a motion vector detection unit for detecting a motion vector associated with the reference block, based on the differences for each of the items of pixel data in relation to the respective multiple candidate blocks operated in the second memory unit, wherein the first memory unit comprises one or more first semiconductor memory blocks, and the second memory unit comprises one or more second semiconductor memory blocks, wherein the first semiconductor memory block has multiple bit lines, multiple word lines perpendicularly crossing the multiple bit lines, and multiple memory cells arranged in a matrix form and connected to the bit lines and the word lines, wherein an area of the multiple memory cells arranged in the matrix form has multiple divisional domains divided in a direction along the word line, wherein each of the multiple selection lines has multiple divisional word lines divided corresponding to the multiple divisional domains, wherein the first semiconductor memory block further has switching mechanism for switching the divisional word lines that are simultaneously activated in the divisional domains, wherein the second semiconductor memory block has multiple bit lines, multiple word lines perpendicularly crossing the multiple bit lines, a reference data input line for receiving reference data, the reference data input lines perpendicularly crossing the bit lines or parallel extending along the bit lines, an operation data output line for outputting operation data, the operation data output lines perpendicularly crossing the multiple the bit lines or parallel extending along the bit lines, a cell selection line for receiving cell selection signal, the cell selection line perpendicularly crossing the multiple word lines or parallel extending along the multiple word lines, multiple memory cells arranged in a matrix form, the cells being connected with the bit lines, the word lines, the reference data input line, the operation data output line, and the cell selection line, and an ancillary operational cell for performing a numerical calculation using at least a part of the operation data outputted from the multiple operation data output line to obtain the differences, wherein the memory cell includes a memory cell unit for storing data of “1” or “0”, a reference data input unit for receiving the reference data, the reference data input unit being connected with the reference data input line, an operation function unit for executing an logical operation using the memory data stored in the memory cell unit and reference data received from the reference data input unit, an operation data output unit for outputting the operation data obtained in the operation function unit to the operation data output line, the operation data output unit being connected with the operation data output line, a cell selection signal input unit for receiving the cell selection signal, the cell selection signal input unit being connected with the cell selection line, and an output control unit for outputting to the operation data output unit the operation data obtained by the operation in the operation function unit, based on the cell selection signal received in the cell selection signal input unit, wherein an area of the multiple memory cells arranged in the matrix form has multiple divisional domains divided in a direction along the cell selection line, wherein each of the multiple selection lines has the multiple divisional cell selection lines divided corresponding to the multiple divisional domains, and wherein the second semiconductor memory block further has switching mechanism for switching the divisional cell selection lines that are simultaneously activated in the associated divisional domain.

A motion compensation predictive encoder according to the invention makes motion compensation using a motion vector detected by the above motion vector detector.

In this invention, the memory device comprises one or more memory blocks. The memory block has a memory cell array consisting of multiple memory cells arranged in a matrix form and multiple selection lines for selecting the respective memory cell columns, the selection line being arranged corresponding to each of the memory cell columns in one direction of the matrix of the memory cell array.

For example, the memory block includes multiple bit lines, multiple word lines perpendicularly crossing the multiple bit lines, multiple memory cells arranged in a matrix form, the cells being connected with the bit lines and the word lines. The above multiple selection lines are word lines and the above one direction of the matrix is a direction along the word line.

Further, the memory block includes multiple bit lines, multiple word lines perpendicularly crossing the multiple bit lines, a reference data input line for receiving reference data, the reference data input line perpendicularly crossing the multiple bit lines or parallel extending along the multiple bit lines, an operation data output line for outputting operation data, the operation data output line perpendicularly crossing the multiple the bit lines or parallel extending along the multiple bit lines, a cell selection line for receiving cell selection signal, the cell selection line perpendicularly crossing the multiple word lines or parallel extending along the multiple bit lines, and multiple memory cells arranged in the matrix form, the cells being connected with the bit lines, the word lines, the reference data input line, the operation data output line, and the cell selection line, wherein the memory cell includes a memory cell unit for storing data of “1” or “0”, a reference data input unit for receiving the reference data, the reference data input unit being connected with the reference data input line, an operation function unit for performing an logical operation using the memory data stored in the memory cell unit and reference data received from the reference data input unit, an operation data output unit for outputting the operation data obtained in the operation function unit to the operation data output line, the operation data output unit being connected with the operation data output line, a cell selection signal input unit for receiving the cell selection signal, the cell selection signal input unit being connected with the cell selection line, and an output control unit for outputting to the operation data output unit the operation data obtained by the operation in the operation function unit, based on the cell selection signal received in the cell selection signal input unit, wherein the multiple selection lines are the multiple cell selection lines, and wherein the one direction of matrix is a direction along the cell selection line.

In this instance, the logical operation is performed in the operation function unit of the memory cell on the memory data stored in memory cell unit and the reference data received from the reference data input unit, and the resultant operation data is outputted from the operation function unit to the operation data output unit upon receipt of a cell selection signal input to the cell selection signal input unit. In the ancillary operational cell, numerical calculation is made using the operation data outputted to the operation data output unit of the memory cell to output the resultant operation data to the operation data output unit.

For example, multiple logical operations are performed in parallel in the operation function unit of the memory cell, while numerical calculations are performed in the operation unit of the ancillary operational cell using multiple items of the resultant operation data obtained by the multiple logical operations.