Video codec with shared interpolation filter and method for use therewith

The present application is related the following applications:

application Ser. No. 11/716,773, entitled, VIDEO PROCESSING SYSTEM AND DEVICE WITH ENCODING AND DECODING MODES AND METHOD FOR USE THEREWITH, filed on Mar. 12, 2007; and

application Ser. No. ______, entitled, VIDEO CODEC WITH SHARED INTRA-PREDICTION MODULE AND METHOD FOR USE THEREWITH, filed on ______.

The present invention relates to encoding used in devices such as video encoders/decoders.

Video encoding has become an important issue for modern video processing devices. Robust encoding algorithms allow video signals to be transmitted with reduced bandwidth and stored in less memory. However, the accuracy of these encoding methods face the scrutiny of users that are becoming accustomed to greater resolution and higher picture quality. Standards have been promulgated for many encoding methods including the H.264 standard that is also referred to as MPEG-4, part 10 or Advanced Video Coding, (AVC). While this standard sets forth many powerful techniques, further improvements are possible to improve the performance and speed of implementation of such methods. The video signal encoded by these encoding methods must be similarly decoded for playback on most video display devices.

The efficient encoding and decoding of video signals and the efficient implementation of encoder and decoders is important to the implementation of many video devices, particularly video devices that are destined for home use. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIGS. 1-3 present pictorial diagram representations of various video devices in accordance with embodiments of the present invention.

FIG. 4 presents a block diagram representation of a video device in accordance with an embodiment of the present invention.

FIG. 5 presents a block diagram representation of a video encoder/decoder 102 in accordance with an embodiment of the present invention.

FIG. 6 presents a graphical representation of macroblock pixels and interpolated pixels in accordance with an embodiment of the present invention.

FIG. 7 presents a block flow diagram of a video encoding operation in accordance with an embodiment of the present invention.

FIG. 8 presents a block flow diagram of a video decoding operation in accordance with an embodiment of the present invention.

FIG. 9 presents a graphical representation of the relationship between example top frame and bottom frame macroblocks (250, 252) and example top field and bottom field macroblocks (254, 256) in accordance with an embodiment of the present invention.

FIG. 10 presents a graphical representation that shows example macroblock partitioning in accordance with an embodiment of the present invention.

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